Power supply noise evaluation with on-chip noise monitoring for various decoupling schemes of SiP

Takafumi Okumura, Yoshiaki Oizono, Yoshitaka Nabeshima, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Power integrity design is a critical issue in system-in-packages (SiP's). In particular, power supply disturbance excited by simultaneous switching output (SSO) noise, or core circuits is serious in a 3D stacked die packages. Therefore, decoupling schemes in such SiP's must be carefully designed to reduce the impedance of power distribution network (PDN) as low as possible up to high frequency range and to avoid the parallel resonance occurred by chip-package connection. In this paper, a test chip was designed and fabricated to generate noise and to monitor on-chip power supply noise. Then, a power noise evaluation system has been established. Power supply noise on core circuits was measured with a noise monitoring circuit. The noise on output buffer circuit was measured by a fixed high/low method. Power supply noises were examined in various decoupling schemes. They are with embedded SMD capacitors inside interposer, and SMD capacitors mounted on the backside of interposer along with on-chip capacitance.

Original languageEnglish
Title of host publication2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010
DOIs
Publication statusPublished - 2010
Event2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010 - Singapore
Duration: 2010 Dec 72010 Dec 9

Other

Other2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010
CitySingapore
Period10/12/710/12/9

Fingerprint

Surface mount technology
Networks (circuits)
Monitoring
Capacitors
Buffer circuits
Electric power distribution
Capacitance
System-in-package

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Okumura, T., Oizono, Y., Nabeshima, Y., & Sudo, T. (2010). Power supply noise evaluation with on-chip noise monitoring for various decoupling schemes of SiP. In 2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010 [5682992] https://doi.org/10.1109/EDAPS.2010.5682992

Power supply noise evaluation with on-chip noise monitoring for various decoupling schemes of SiP. / Okumura, Takafumi; Oizono, Yoshiaki; Nabeshima, Yoshitaka; Sudo, Toshio.

2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010. 2010. 5682992.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Okumura, T, Oizono, Y, Nabeshima, Y & Sudo, T 2010, Power supply noise evaluation with on-chip noise monitoring for various decoupling schemes of SiP. in 2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010., 5682992, 2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010, Singapore, 10/12/7. https://doi.org/10.1109/EDAPS.2010.5682992
Okumura T, Oizono Y, Nabeshima Y, Sudo T. Power supply noise evaluation with on-chip noise monitoring for various decoupling schemes of SiP. In 2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010. 2010. 5682992 https://doi.org/10.1109/EDAPS.2010.5682992
Okumura, Takafumi ; Oizono, Yoshiaki ; Nabeshima, Yoshitaka ; Sudo, Toshio. / Power supply noise evaluation with on-chip noise monitoring for various decoupling schemes of SiP. 2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010. 2010.
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