Power supply noise suppression by optimizing on-die PDN impedance

Yoshinori Kobayashi, Ryota Kobayashi, Tatsuya Mido, Genki Kubo, Hiroki Otsuka, Hideyuki Fujii, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Power integrity design has been becoming important in the advanced CMOS digital systems, because power supply noise induces logic instability and electromagnetic radiation. Especially, anti-resonance peaks in power distribution network (PDN) due to the chip-package interaction induce the unwanted power supply fluctuation, and result in large electromagnetic radiation. In this paper, effects of damping condition of the total PDN impedance on power supply noise have been studied by adding variable on-die RC circuit to the intrinsic on-die RC circuit in chip PDN. Two types of test chips were designed with different variable on-die PDN impedances. By varying the values of on-die RC circuit, the simulated waveforms of power supply noises for the two test chips have been changed from oscillatory region to damped regions.

Original languageEnglish
Title of host publication2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012 - Kyoto, Japan
Duration: 2012 Dec 102012 Dec 12

Publication series

Name2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012

Conference

Conference2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
CountryJapan
CityKyoto
Period12/12/1012/12/12

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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