Realization of simple decoders for high-coding-rate convolutional codes

Katsuhiko Kawazoe, Shuji Kubota

Research output: Contribution to journalArticle

Abstract

This paper describes a method to configure pre-decoders for the high coding rate convolution codes needed when the SST method is used, thus enabling low power consumption in a Viterbi decoder. The proposed pre-decoders have no correcting capability, but do allow decoding of convolution codes with a minimum of hardware. The configuration method is studied here for general convolution codes with a constraint length K and a coding rate n/m. A specific circuit configuration for a pre-decoder is presented for the commonly used, punctured type, high coding rate convolution codes with coding rates 3/4 to 7/8 and 15/16. The use of the SST method is now possible for high coding rate codes. The gate operates with a coding rate of 7/8 and an error rate after decoding of 10-4 that is 40% of that in the conventional type. Hence, a low power consumption Viterbi decoder is possible. As an example of the proposed high coding rate pre-decoder, a high-speed transmission error rate estimation circuit is proposed and its characteristics are obtained.

Original languageEnglish
Pages (from-to)47-56
Number of pages10
JournalElectronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi)
Volume81
Issue number3
Publication statusPublished - 1998 Mar
Externally publishedYes

Fingerprint

Convolutional codes
Convolution
Decoding
Electric power utilization
Networks (circuits)
Hardware

Keywords

  • Convolution code
  • Error correction
  • LSI
  • Viterbi decoding

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

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title = "Realization of simple decoders for high-coding-rate convolutional codes",
abstract = "This paper describes a method to configure pre-decoders for the high coding rate convolution codes needed when the SST method is used, thus enabling low power consumption in a Viterbi decoder. The proposed pre-decoders have no correcting capability, but do allow decoding of convolution codes with a minimum of hardware. The configuration method is studied here for general convolution codes with a constraint length K and a coding rate n/m. A specific circuit configuration for a pre-decoder is presented for the commonly used, punctured type, high coding rate convolution codes with coding rates 3/4 to 7/8 and 15/16. The use of the SST method is now possible for high coding rate codes. The gate operates with a coding rate of 7/8 and an error rate after decoding of 10-4 that is 40{\%} of that in the conventional type. Hence, a low power consumption Viterbi decoder is possible. As an example of the proposed high coding rate pre-decoder, a high-speed transmission error rate estimation circuit is proposed and its characteristics are obtained.",
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N2 - This paper describes a method to configure pre-decoders for the high coding rate convolution codes needed when the SST method is used, thus enabling low power consumption in a Viterbi decoder. The proposed pre-decoders have no correcting capability, but do allow decoding of convolution codes with a minimum of hardware. The configuration method is studied here for general convolution codes with a constraint length K and a coding rate n/m. A specific circuit configuration for a pre-decoder is presented for the commonly used, punctured type, high coding rate convolution codes with coding rates 3/4 to 7/8 and 15/16. The use of the SST method is now possible for high coding rate codes. The gate operates with a coding rate of 7/8 and an error rate after decoding of 10-4 that is 40% of that in the conventional type. Hence, a low power consumption Viterbi decoder is possible. As an example of the proposed high coding rate pre-decoder, a high-speed transmission error rate estimation circuit is proposed and its characteristics are obtained.

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