Reduction of buffer-related current collapse in GaN FETs under favour of a field plate

K. Itagaki, A. Nakajima, Kazushige Horio

Research output: Contribution to journalArticle

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Abstract

Two-dimensional transient analysis of GaN MESFETs with a semi-insulating buffer layer is performed in which a deep donor and a deep acceptor are considered in the buffer layer, and the results are compared between the two cases with and without a field plate. It is shown that buffer-related drain lag is reduced by introducing a field plate because trapping effects become smaller. It is also shown that current collapse and gate lag are also reduced in the field-plate structure. The dependence on SiN passivation layer thickness is also studied, indicating that there is an optimum SiN thickness to minimize the buffer-related current collapse and drain lag in GaN-based FETs.

Original languageEnglish
Pages (from-to)2976-2978
Number of pages3
JournalPhysica Status Solidi (C) Current Topics in Solid State Physics
Volume5
Issue number9
DOIs
Publication statusPublished - 2008

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field effect transistors
buffers
time lag
passivity
trapping

ASJC Scopus subject areas

  • Condensed Matter Physics

Cite this

Reduction of buffer-related current collapse in GaN FETs under favour of a field plate. / Itagaki, K.; Nakajima, A.; Horio, Kazushige.

In: Physica Status Solidi (C) Current Topics in Solid State Physics, Vol. 5, No. 9, 2008, p. 2976-2978.

Research output: Contribution to journalArticle

@article{d1314cc9c55e4c07bcb13d0f1cba8009,
title = "Reduction of buffer-related current collapse in GaN FETs under favour of a field plate",
abstract = "Two-dimensional transient analysis of GaN MESFETs with a semi-insulating buffer layer is performed in which a deep donor and a deep acceptor are considered in the buffer layer, and the results are compared between the two cases with and without a field plate. It is shown that buffer-related drain lag is reduced by introducing a field plate because trapping effects become smaller. It is also shown that current collapse and gate lag are also reduced in the field-plate structure. The dependence on SiN passivation layer thickness is also studied, indicating that there is an optimum SiN thickness to minimize the buffer-related current collapse and drain lag in GaN-based FETs.",
author = "K. Itagaki and A. Nakajima and Kazushige Horio",
year = "2008",
doi = "10.1002/pssc.200779155",
language = "English",
volume = "5",
pages = "2976--2978",
journal = "Physica Status Solidi (C) Current Topics in Solid State Physics",
issn = "1862-6351",
publisher = "Wiley-VCH Verlag",
number = "9",

}

TY - JOUR

T1 - Reduction of buffer-related current collapse in GaN FETs under favour of a field plate

AU - Itagaki, K.

AU - Nakajima, A.

AU - Horio, Kazushige

PY - 2008

Y1 - 2008

N2 - Two-dimensional transient analysis of GaN MESFETs with a semi-insulating buffer layer is performed in which a deep donor and a deep acceptor are considered in the buffer layer, and the results are compared between the two cases with and without a field plate. It is shown that buffer-related drain lag is reduced by introducing a field plate because trapping effects become smaller. It is also shown that current collapse and gate lag are also reduced in the field-plate structure. The dependence on SiN passivation layer thickness is also studied, indicating that there is an optimum SiN thickness to minimize the buffer-related current collapse and drain lag in GaN-based FETs.

AB - Two-dimensional transient analysis of GaN MESFETs with a semi-insulating buffer layer is performed in which a deep donor and a deep acceptor are considered in the buffer layer, and the results are compared between the two cases with and without a field plate. It is shown that buffer-related drain lag is reduced by introducing a field plate because trapping effects become smaller. It is also shown that current collapse and gate lag are also reduced in the field-plate structure. The dependence on SiN passivation layer thickness is also studied, indicating that there is an optimum SiN thickness to minimize the buffer-related current collapse and drain lag in GaN-based FETs.

UR - http://www.scopus.com/inward/record.url?scp=77951270551&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77951270551&partnerID=8YFLogxK

U2 - 10.1002/pssc.200779155

DO - 10.1002/pssc.200779155

M3 - Article

VL - 5

SP - 2976

EP - 2978

JO - Physica Status Solidi (C) Current Topics in Solid State Physics

JF - Physica Status Solidi (C) Current Topics in Solid State Physics

SN - 1862-6351

IS - 9

ER -