SCARCE-STATE-TRANSITION VITERBI-DECODER VLSI FOR BIT ERROR CORRECTION.

Tsunehachi Ishitani, Kazuo Tansho, Norio Miyahara, Shuji Kubota, Shuzo Kato

Research output: Contribution to journalArticle

23 Citations (Scopus)

Abstract

A high-speed Viterbi decoder VLSI with coding rate R equals 1/2 and constraint length K equals 7 for bit-error correction has been developed using 1. 5 mu m n-well CMOS technology. To reduce both hardware size and power dissipation, a recently developed scarce-state-transition (SST) Viterbi decoding scheme has been utilized. In addition, three-layer metallization and an advanced hierarchical macrocell design method (HMCM) have been adopted to improve packing density and reduce chip size. As a result, active chip area has been reduced by half, compared to the conventional standard cell design method (SCM) with two-layer metallization, and 42K gates have been integrated on a chip with a die size of 9. 52 multiplied by 10. 0 mm**2. The VLSI decoder has achieved a maximum data throughput rate of 23 Mb/s with a net coding gain of 4. 4 dB (at 10** minus **4 bit-error rate). The chip dissipates only 825 mW at a data rate of 10 Mb/s.

Original languageEnglish
Pages (from-to)575-582
Number of pages8
JournalIEEE Journal of Solid-State Circuits
VolumeSC-22
Issue number4
Publication statusPublished - 1987 Aug
Externally publishedYes

Fingerprint

Error correction
Metallizing
Bit error rate
Decoding
Energy dissipation
Throughput
Hardware

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Ishitani, T., Tansho, K., Miyahara, N., Kubota, S., & Kato, S. (1987). SCARCE-STATE-TRANSITION VITERBI-DECODER VLSI FOR BIT ERROR CORRECTION. IEEE Journal of Solid-State Circuits, SC-22(4), 575-582.

SCARCE-STATE-TRANSITION VITERBI-DECODER VLSI FOR BIT ERROR CORRECTION. / Ishitani, Tsunehachi; Tansho, Kazuo; Miyahara, Norio; Kubota, Shuji; Kato, Shuzo.

In: IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 4, 08.1987, p. 575-582.

Research output: Contribution to journalArticle

Ishitani, T, Tansho, K, Miyahara, N, Kubota, S & Kato, S 1987, 'SCARCE-STATE-TRANSITION VITERBI-DECODER VLSI FOR BIT ERROR CORRECTION.', IEEE Journal of Solid-State Circuits, vol. SC-22, no. 4, pp. 575-582.
Ishitani, Tsunehachi ; Tansho, Kazuo ; Miyahara, Norio ; Kubota, Shuji ; Kato, Shuzo. / SCARCE-STATE-TRANSITION VITERBI-DECODER VLSI FOR BIT ERROR CORRECTION. In: IEEE Journal of Solid-State Circuits. 1987 ; Vol. SC-22, No. 4. pp. 575-582.
@article{660a89bbd2dd4bd5a7a0ae054da9a512,
title = "SCARCE-STATE-TRANSITION VITERBI-DECODER VLSI FOR BIT ERROR CORRECTION.",
abstract = "A high-speed Viterbi decoder VLSI with coding rate R equals 1/2 and constraint length K equals 7 for bit-error correction has been developed using 1. 5 mu m n-well CMOS technology. To reduce both hardware size and power dissipation, a recently developed scarce-state-transition (SST) Viterbi decoding scheme has been utilized. In addition, three-layer metallization and an advanced hierarchical macrocell design method (HMCM) have been adopted to improve packing density and reduce chip size. As a result, active chip area has been reduced by half, compared to the conventional standard cell design method (SCM) with two-layer metallization, and 42K gates have been integrated on a chip with a die size of 9. 52 multiplied by 10. 0 mm**2. The VLSI decoder has achieved a maximum data throughput rate of 23 Mb/s with a net coding gain of 4. 4 dB (at 10** minus **4 bit-error rate). The chip dissipates only 825 mW at a data rate of 10 Mb/s.",
author = "Tsunehachi Ishitani and Kazuo Tansho and Norio Miyahara and Shuji Kubota and Shuzo Kato",
year = "1987",
month = "8",
language = "English",
volume = "SC-22",
pages = "575--582",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

TY - JOUR

T1 - SCARCE-STATE-TRANSITION VITERBI-DECODER VLSI FOR BIT ERROR CORRECTION.

AU - Ishitani, Tsunehachi

AU - Tansho, Kazuo

AU - Miyahara, Norio

AU - Kubota, Shuji

AU - Kato, Shuzo

PY - 1987/8

Y1 - 1987/8

N2 - A high-speed Viterbi decoder VLSI with coding rate R equals 1/2 and constraint length K equals 7 for bit-error correction has been developed using 1. 5 mu m n-well CMOS technology. To reduce both hardware size and power dissipation, a recently developed scarce-state-transition (SST) Viterbi decoding scheme has been utilized. In addition, three-layer metallization and an advanced hierarchical macrocell design method (HMCM) have been adopted to improve packing density and reduce chip size. As a result, active chip area has been reduced by half, compared to the conventional standard cell design method (SCM) with two-layer metallization, and 42K gates have been integrated on a chip with a die size of 9. 52 multiplied by 10. 0 mm**2. The VLSI decoder has achieved a maximum data throughput rate of 23 Mb/s with a net coding gain of 4. 4 dB (at 10** minus **4 bit-error rate). The chip dissipates only 825 mW at a data rate of 10 Mb/s.

AB - A high-speed Viterbi decoder VLSI with coding rate R equals 1/2 and constraint length K equals 7 for bit-error correction has been developed using 1. 5 mu m n-well CMOS technology. To reduce both hardware size and power dissipation, a recently developed scarce-state-transition (SST) Viterbi decoding scheme has been utilized. In addition, three-layer metallization and an advanced hierarchical macrocell design method (HMCM) have been adopted to improve packing density and reduce chip size. As a result, active chip area has been reduced by half, compared to the conventional standard cell design method (SCM) with two-layer metallization, and 42K gates have been integrated on a chip with a die size of 9. 52 multiplied by 10. 0 mm**2. The VLSI decoder has achieved a maximum data throughput rate of 23 Mb/s with a net coding gain of 4. 4 dB (at 10** minus **4 bit-error rate). The chip dissipates only 825 mW at a data rate of 10 Mb/s.

UR - http://www.scopus.com/inward/record.url?scp=0023399884&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023399884&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0023399884

VL - SC-22

SP - 575

EP - 582

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 4

ER -