Selective multi-threshold technique for high-performance and low-standby applications

In portable applications such as W-CDMA cell phones, high performance and low standby leakage are both required. We propose an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-V_th transistors and high-V_th sleep transistors are newly introduced. MT cells are assigned to critical paths to speed up, while High-V_th cells are assigned to non-critical paths to reduce leakage. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core for W-CDMA baseband LSI. The worst path-delay was improved by 14% over the single high-V_th design without increasing standby leakage at 10% area overhead.