Signal integrity characterization of high-speed DDR interface

Takuya Kato, Shintaro Yamamoto, Toshio Sudo, Yasushi Ono, Eiji Takahashi, Toru Yamada

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

With the increase of the clock speed of memory systems, signal integrity is becoming more an important design issue to ensure system reliability. DDR2 memory systems adopt on-die termination scheme to reduce reflection noise on a transmission lines. This paper describes a correct prediction method of waveforms at the receiver chip from the waveforms at the vicinity of the packaged chip.

Original languageEnglish
Title of host publication2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
DOIs
Publication statusPublished - 2011 Dec 1
Event2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011 - Hanzhou, China
Duration: 2011 Dec 122011 Dec 14

Publication series

Name2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011

Conference

Conference2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
CountryChina
CityHanzhou
Period11/12/1211/12/14

Keywords

  • DDR2 memory
  • S parameter
  • TDR
  • signal integrity

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Kato, T., Yamamoto, S., Sudo, T., Ono, Y., Takahashi, E., & Yamada, T. (2011). Signal integrity characterization of high-speed DDR interface. In 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011 [6213776] (2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011). https://doi.org/10.1109/EDAPS.2011.6213776