Signal integrity characterization of high-speed DDR interface

Takuya Kato; Shintaro Yamamoto; Toshio Sudo; Yasushi Ono; Eiji Takahashi; Toru Yamada

doi:10.1109/EDAPS.2011.6213776

Signal integrity characterization of high-speed DDR interface

Takuya Kato, Shintaro Yamamoto, Toshio Sudo, Yasushi Ono, Eiji Takahashi, Toru Yamada

Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

With the increase of the clock speed of memory systems, signal integrity is becoming more an important design issue to ensure system reliability. DDR2 memory systems adopt on-die termination scheme to reduce reflection noise on a transmission lines. This paper describes a correct prediction method of waveforms at the receiver chip from the waveforms at the vicinity of the packaged chip.

Original language	English
Title of host publication	2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
DOIs	https://doi.org/10.1109/EDAPS.2011.6213776
Publication status	Published - 2011 Dec 1
Event	2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011 - Hanzhou, China Duration: 2011 Dec 12 → 2011 Dec 14

Publication series

Name	2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011

Conference

Conference	2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
Country/Territory	China
City	Hanzhou
Period	11/12/12 → 11/12/14

Keywords

DDR2 memory
S parameter
TDR
signal integrity

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/EDAPS.2011.6213776

Cite this

Signal integrity characterization of high-speed DDR interface. / Kato, Takuya; Yamamoto, Shintaro; Sudo, Toshio et al.

2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011. 2011. 6213776 (2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kato, T, Yamamoto, S, Sudo, T, Ono, Y, Takahashi, E & Yamada, T 2011, Signal integrity characterization of high-speed DDR interface. in 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011., 6213776, 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011, 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011, Hanzhou, China, 11/12/12. https://doi.org/10.1109/EDAPS.2011.6213776

@inproceedings{4def6dba54504060bfa915d80f17db81,

title = "Signal integrity characterization of high-speed DDR interface",

abstract = "With the increase of the clock speed of memory systems, signal integrity is becoming more an important design issue to ensure system reliability. DDR2 memory systems adopt on-die termination scheme to reduce reflection noise on a transmission lines. This paper describes a correct prediction method of waveforms at the receiver chip from the waveforms at the vicinity of the packaged chip.",

keywords = "DDR2 memory, S parameter, TDR, signal integrity",

author = "Takuya Kato and Shintaro Yamamoto and Toshio Sudo and Yasushi Ono and Eiji Takahashi and Toru Yamada",

year = "2011",

month = dec,

day = "1",

doi = "10.1109/EDAPS.2011.6213776",

language = "English",

isbn = "9781467322881",

series = "2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011",

booktitle = "2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011",

note = "2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011 ; Conference date: 12-12-2011 Through 14-12-2011",

}

TY - GEN

T1 - Signal integrity characterization of high-speed DDR interface

AU - Kato, Takuya

AU - Yamamoto, Shintaro

AU - Sudo, Toshio

AU - Ono, Yasushi

AU - Takahashi, Eiji

AU - Yamada, Toru

PY - 2011/12/1

Y1 - 2011/12/1

N2 - With the increase of the clock speed of memory systems, signal integrity is becoming more an important design issue to ensure system reliability. DDR2 memory systems adopt on-die termination scheme to reduce reflection noise on a transmission lines. This paper describes a correct prediction method of waveforms at the receiver chip from the waveforms at the vicinity of the packaged chip.

AB - With the increase of the clock speed of memory systems, signal integrity is becoming more an important design issue to ensure system reliability. DDR2 memory systems adopt on-die termination scheme to reduce reflection noise on a transmission lines. This paper describes a correct prediction method of waveforms at the receiver chip from the waveforms at the vicinity of the packaged chip.

KW - DDR2 memory

KW - S parameter

KW - TDR

KW - signal integrity

UR - http://www.scopus.com/inward/record.url?scp=84864249460&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84864249460&partnerID=8YFLogxK

U2 - 10.1109/EDAPS.2011.6213776

DO - 10.1109/EDAPS.2011.6213776

M3 - Conference contribution

AN - SCOPUS:84864249460

SN - 9781467322881

T3 - 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011

BT - 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011

T2 - 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011

Y2 - 12 December 2011 through 14 December 2011

ER -

Signal integrity characterization of high-speed DDR interface

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this