Simulation of recess-structure dependence of gate-lag phenomena in GaAs MESFETs

K. Horio, Y. Mitani, A. Wakabayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We have made two-dimensional simulation of turn-on characteristics of recessed-gate and buried-gate GaAs MESFETs, and studied how the gate-lag or the slow current transient (which may occur due to surface states) is affected by the recess-structural parameters and the off-state gate voltage V Goff. It is shown that when VGoff is around the threshold voltage (pinch-off voltage) Vth, the gate-lag could be greatly reduced by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when VGoff is much more negative than Vth.

Original languageEnglish
Title of host publication2001 International Conference on Modeling and Simulation of Microsystems - MSM 2001
EditorsM. Laudon, B. Romanowicz
Pages510-513
Number of pages4
Publication statusPublished - 2001 Dec 1
Event2001 International Conference on Modeling and Simulation of Microsystems - MSM 2001 - Hilton Head Island, SC, United States
Duration: 2001 Mar 192001 Mar 21

Publication series

Name2001 International Conference on Modeling and Simulation of Microsystems - MSM 2001

Conference

Conference2001 International Conference on Modeling and Simulation of Microsystems - MSM 2001
CountryUnited States
CityHilton Head Island, SC
Period01/3/1901/3/21

Keywords

  • Buried gate
  • GaAs MESFET
  • Gate lag
  • Recessed gate
  • Surface state

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Horio, K., Mitani, Y., & Wakabayashi, A. (2001). Simulation of recess-structure dependence of gate-lag phenomena in GaAs MESFETs. In M. Laudon, & B. Romanowicz (Eds.), 2001 International Conference on Modeling and Simulation of Microsystems - MSM 2001 (pp. 510-513). (2001 International Conference on Modeling and Simulation of Microsystems - MSM 2001).