Simulation of slow current transients and current compression in AlGaAs/GaAs HFETs

H. Ikarashi, K. Kitamura, N. Kurosawa, Kazushige Horio

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Two-dimensional transient simulations of AlGaAs/GaAs HFETs are performed in which substrate traps and surface states are considered. When the drain voltage is raised abruptly, the drain current overshoots the steady-state value, and when it is lowered abruptly, the drain current remains at a low value, showing drain-lag behavior. Turn-on characteristics are also calculated when both the gate voltage and the drain voltage are changed abruptly, and quasi-pulsed I-V curves are derived from them. It is shown that the drain lag due to substrate traps could become a cause of so-called current compression of the HFETs. It is also shown that gate lag due to surface states could become a major cause of the current compression.

Original languageEnglish
Pages (from-to)357-360
Number of pages4
JournalJournal of Computational Electronics
Volume5
Issue number4
DOIs
Publication statusPublished - 2006 Dec

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aluminum gallium arsenides
Drain current
Surface states
time lag
Electric potential
electric potential
simulation
traps
Substrates
causes
gallium arsenide
curves

Keywords

  • AlGaAs/GaAs HFET
  • Current compression
  • Drain lag
  • Gate lag
  • Trap

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Electrical and Electronic Engineering

Cite this

Simulation of slow current transients and current compression in AlGaAs/GaAs HFETs. / Ikarashi, H.; Kitamura, K.; Kurosawa, N.; Horio, Kazushige.

In: Journal of Computational Electronics, Vol. 5, No. 4, 12.2006, p. 357-360.

Research output: Contribution to journalArticle

@article{03343e189b3c464bba15b2203da1b0ea,
title = "Simulation of slow current transients and current compression in AlGaAs/GaAs HFETs",
abstract = "Two-dimensional transient simulations of AlGaAs/GaAs HFETs are performed in which substrate traps and surface states are considered. When the drain voltage is raised abruptly, the drain current overshoots the steady-state value, and when it is lowered abruptly, the drain current remains at a low value, showing drain-lag behavior. Turn-on characteristics are also calculated when both the gate voltage and the drain voltage are changed abruptly, and quasi-pulsed I-V curves are derived from them. It is shown that the drain lag due to substrate traps could become a cause of so-called current compression of the HFETs. It is also shown that gate lag due to surface states could become a major cause of the current compression.",
keywords = "AlGaAs/GaAs HFET, Current compression, Drain lag, Gate lag, Trap",
author = "H. Ikarashi and K. Kitamura and N. Kurosawa and Kazushige Horio",
year = "2006",
month = "12",
doi = "10.1007/s10825-006-0025-6",
language = "English",
volume = "5",
pages = "357--360",
journal = "Journal of Computational Electronics",
issn = "1569-8025",
publisher = "Springer Netherlands",
number = "4",

}

TY - JOUR

T1 - Simulation of slow current transients and current compression in AlGaAs/GaAs HFETs

AU - Ikarashi, H.

AU - Kitamura, K.

AU - Kurosawa, N.

AU - Horio, Kazushige

PY - 2006/12

Y1 - 2006/12

N2 - Two-dimensional transient simulations of AlGaAs/GaAs HFETs are performed in which substrate traps and surface states are considered. When the drain voltage is raised abruptly, the drain current overshoots the steady-state value, and when it is lowered abruptly, the drain current remains at a low value, showing drain-lag behavior. Turn-on characteristics are also calculated when both the gate voltage and the drain voltage are changed abruptly, and quasi-pulsed I-V curves are derived from them. It is shown that the drain lag due to substrate traps could become a cause of so-called current compression of the HFETs. It is also shown that gate lag due to surface states could become a major cause of the current compression.

AB - Two-dimensional transient simulations of AlGaAs/GaAs HFETs are performed in which substrate traps and surface states are considered. When the drain voltage is raised abruptly, the drain current overshoots the steady-state value, and when it is lowered abruptly, the drain current remains at a low value, showing drain-lag behavior. Turn-on characteristics are also calculated when both the gate voltage and the drain voltage are changed abruptly, and quasi-pulsed I-V curves are derived from them. It is shown that the drain lag due to substrate traps could become a cause of so-called current compression of the HFETs. It is also shown that gate lag due to surface states could become a major cause of the current compression.

KW - AlGaAs/GaAs HFET

KW - Current compression

KW - Drain lag

KW - Gate lag

KW - Trap

UR - http://www.scopus.com/inward/record.url?scp=34248639839&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34248639839&partnerID=8YFLogxK

U2 - 10.1007/s10825-006-0025-6

DO - 10.1007/s10825-006-0025-6

M3 - Article

VL - 5

SP - 357

EP - 360

JO - Journal of Computational Electronics

JF - Journal of Computational Electronics

SN - 1569-8025

IS - 4

ER -