Simulation of surface and buffer trapping effects on gate lag in AlGaN/GaN HEMTs

K. Horio, A. Nakajima, K. Fujii

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Two-dimensional analysis of turn-on characteristics of AlGaN/GaN HEMTs is performed in which both buffer traps and surface states (traps) are considered. It is studied how so-called gate lag is affected by these traps. It is shown that gate lag due to buffer traps can occur because in the off state, electrons are injected into the buffer layer and captured by the traps. It is also shown that gate lag due to an electron-trap-type surface state can occur only when electron's gate tunneling is considered. Dependence of gate lag on buffer-trap parameters is also studied.

Original languageEnglish
Title of host publicationNanotechnology 2010
Subtitle of host publicationElectronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010
Pages693-696
Number of pages4
Publication statusPublished - 2010 Nov 9
EventNanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010 - Anaheim, CA, United States
Duration: 2010 Jun 212010 Jun 24

Publication series

NameNanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010
Volume2

Conference

ConferenceNanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010
Country/TerritoryUnited States
CityAnaheim, CA
Period10/6/2110/6/24

Keywords

  • AlGaN/GaN HEMT
  • Gate lag
  • Gate tunneling
  • Surface state
  • Trap

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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