SLD-1(Silent Large Datapath)

A ultra low power reconfigurable accelerator

Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura, Masaaki Kondo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

SLD(Silent Large Datapath)-1 is a prototype accelerator for media processing consisting of a large Processing Element (PE) array which includes 24bit 8 × 8 PEs with combinatorial circuits and a small micro-controller for data memory access. It was fabricated in 2.1mm 4.2mm × 65 nm CMOS, and achieves 1.356GOPS/11mW sustained performance by reducing overhead of clock tree and the benefit of voltage scaling.

Original languageEnglish
Title of host publicationIEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings
DOIs
Publication statusPublished - 2011
Event14th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XIV - Yokohama
Duration: 2011 Apr 202011 Apr 22

Other

Other14th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XIV
CityYokohama
Period11/4/2011/4/22

Fingerprint

Particle accelerators
Combinatorial circuits
Processing
Clocks
Data storage equipment
Controllers
Voltage scaling

Keywords

  • 65nmCMOS
  • Low Power
  • Reconfigurable System

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H., & Kondo, M. (2011). SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. In IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings [5890918] https://doi.org/10.1109/COOLCHIPS.2011.5890918

SLD-1(Silent Large Datapath) : A ultra low power reconfigurable accelerator. / Ozaki, Nobuaki; Usami, Kimiyoshi; Amano, Hideharu; Namiki, Mitaro; Nakamura, Hiroshi; Kondo, Masaaki.

IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 2011. 5890918.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ozaki, N, Usami, K, Amano, H, Namiki, M, Nakamura, H & Kondo, M 2011, SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. in IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings., 5890918, 14th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XIV, Yokohama, 11/4/20. https://doi.org/10.1109/COOLCHIPS.2011.5890918
Ozaki N, Usami K, Amano H, Namiki M, Nakamura H, Kondo M. SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. In IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 2011. 5890918 https://doi.org/10.1109/COOLCHIPS.2011.5890918
Ozaki, Nobuaki ; Usami, Kimiyoshi ; Amano, Hideharu ; Namiki, Mitaro ; Nakamura, Hiroshi ; Kondo, Masaaki. / SLD-1(Silent Large Datapath) : A ultra low power reconfigurable accelerator. IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 2011.
@inproceedings{683ff7e9d7d942f0a7e9989ad88bdcaa,
title = "SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator",
abstract = "SLD(Silent Large Datapath)-1 is a prototype accelerator for media processing consisting of a large Processing Element (PE) array which includes 24bit 8 × 8 PEs with combinatorial circuits and a small micro-controller for data memory access. It was fabricated in 2.1mm 4.2mm × 65 nm CMOS, and achieves 1.356GOPS/11mW sustained performance by reducing overhead of clock tree and the benefit of voltage scaling.",
keywords = "65nmCMOS, Low Power, Reconfigurable System",
author = "Nobuaki Ozaki and Kimiyoshi Usami and Hideharu Amano and Mitaro Namiki and Hiroshi Nakamura and Masaaki Kondo",
year = "2011",
doi = "10.1109/COOLCHIPS.2011.5890918",
language = "English",
isbn = "9781612848846",
booktitle = "IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings",

}

TY - GEN

T1 - SLD-1(Silent Large Datapath)

T2 - A ultra low power reconfigurable accelerator

AU - Ozaki, Nobuaki

AU - Usami, Kimiyoshi

AU - Amano, Hideharu

AU - Namiki, Mitaro

AU - Nakamura, Hiroshi

AU - Kondo, Masaaki

PY - 2011

Y1 - 2011

N2 - SLD(Silent Large Datapath)-1 is a prototype accelerator for media processing consisting of a large Processing Element (PE) array which includes 24bit 8 × 8 PEs with combinatorial circuits and a small micro-controller for data memory access. It was fabricated in 2.1mm 4.2mm × 65 nm CMOS, and achieves 1.356GOPS/11mW sustained performance by reducing overhead of clock tree and the benefit of voltage scaling.

AB - SLD(Silent Large Datapath)-1 is a prototype accelerator for media processing consisting of a large Processing Element (PE) array which includes 24bit 8 × 8 PEs with combinatorial circuits and a small micro-controller for data memory access. It was fabricated in 2.1mm 4.2mm × 65 nm CMOS, and achieves 1.356GOPS/11mW sustained performance by reducing overhead of clock tree and the benefit of voltage scaling.

KW - 65nmCMOS

KW - Low Power

KW - Reconfigurable System

UR - http://www.scopus.com/inward/record.url?scp=79960201715&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79960201715&partnerID=8YFLogxK

U2 - 10.1109/COOLCHIPS.2011.5890918

DO - 10.1109/COOLCHIPS.2011.5890918

M3 - Conference contribution

SN - 9781612848846

BT - IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings

ER -