Sub-1 V supply voltage GaAs LSI technology based on 0.25 μm E/D-HJFETs (IS3Ts)

Hikaru Hida, Masatoshi Tokushima, Tadashi Maeda, Masaoki Ishikawa, Muneo Fukaishi, Keiichi Numata, Yasuo Ohno

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

An advantage of lowering the supply voltage for low-power consumption LSIs without sacrificing speed is described, based on switching analysis of an E/D-FET DCFL (Enhancement/Depletion-mode FET Direct-Coupled FET Logic) inverter. This analysis takes into account the effect of current voltage characteristics in the non-saturation regime. New technology of fabricating 0.25 μm gate E/D GaAs Heterojunction (HJ) FET LSIs, which has been developed as a step towards the development of ultra-low supply voltage LSIs, is also described. This technology, which is based upon all dry-process techniques, includes the formation of a 0.25 μm gate opening by optical lithography, and inner SiO2 sidewalls. The fmax and gm max for a Y-shaped gate E-HJFET fabricated by this technology are 108 GHz and 520 mS/mm, respectively. Excellent performance is also obtained with DCFL ring oscillators using n-AlGaAs/i-InGaAs pseudomorphic E/D-HJFETs. These include 18 ps/gate unloaded delay and 109 ps/gate loaded delay (FI = FO = 3, L = 1 mm) with 0.15 mW/gate at 0.6 V, where inverters have a sufficient noise margin of more than 180 mV. In addition, 10 Gbps error-free operation of a selector switch is demonstrated with 9.4 mW at 0.6 V.

Original languageEnglish
Title of host publicationNEC Research and Development
Pages147-156
Number of pages10
Volume36
Edition1
Publication statusPublished - 1995 Jan 1

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Hida, H., Tokushima, M., Maeda, T., Ishikawa, M., Fukaishi, M., Numata, K., & Ohno, Y. (1995). Sub-1 V supply voltage GaAs LSI technology based on 0.25 μm E/D-HJFETs (IS3Ts). In NEC Research and Development (1 ed., Vol. 36, pp. 147-156)