Sub-1 V supply voltage GaAs LSI technology based on 0.25 μm E/D-HJFETs (IS3Ts)

Hikaru Hida, Masatoshi Tokushima, Tadashi Maeda, Masaoki Ishikawa, Muneo Fukaishi, Keiichi Numata, Yasuo Ohno

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

An advantage of lowering the supply voltage for low-power consumption LSIs without sacrificing speed is described, based on switching analysis of an E/D-FET DCFL (Enhancement/Depletion-mode FET Direct-Coupled FET Logic) inverter. This analysis takes into account the effect of current voltage characteristics in the non-saturation regime. New technology of fabricating 0.25 μm gate E/D GaAs Heterojunction (HJ) FET LSIs, which has been developed as a step towards the development of ultra-low supply voltage LSIs, is also described. This technology, which is based upon all dry-process techniques, includes the formation of a 0.25 μm gate opening by optical lithography, and inner SiO2 sidewalls. The fmax and gm max for a Y-shaped gate E-HJFET fabricated by this technology are 108 GHz and 520 mS/mm, respectively. Excellent performance is also obtained with DCFL ring oscillators using n-AlGaAs/i-InGaAs pseudomorphic E/D-HJFETs. These include 18 ps/gate unloaded delay and 109 ps/gate loaded delay (FI = FO = 3, L = 1 mm) with 0.15 mW/gate at 0.6 V, where inverters have a sufficient noise margin of more than 180 mV. In addition, 10 Gbps error-free operation of a selector switch is demonstrated with 9.4 mW at 0.6 V.

Original languageEnglish
Title of host publicationNEC Research and Development
Pages147-156
Number of pages10
Volume36
Edition1
Publication statusPublished - 1995 Jan
Externally publishedYes

Fingerprint

Field effect transistors
Electric potential
Photolithography
Current voltage characteristics
Heterojunctions
Electric power utilization
Switches

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Hida, H., Tokushima, M., Maeda, T., Ishikawa, M., Fukaishi, M., Numata, K., & Ohno, Y. (1995). Sub-1 V supply voltage GaAs LSI technology based on 0.25 μm E/D-HJFETs (IS3Ts). In NEC Research and Development (1 ed., Vol. 36, pp. 147-156)

Sub-1 V supply voltage GaAs LSI technology based on 0.25 μm E/D-HJFETs (IS3Ts). / Hida, Hikaru; Tokushima, Masatoshi; Maeda, Tadashi; Ishikawa, Masaoki; Fukaishi, Muneo; Numata, Keiichi; Ohno, Yasuo.

NEC Research and Development. Vol. 36 1. ed. 1995. p. 147-156.

Research output: Chapter in Book/Report/Conference proceedingChapter

Hida, H, Tokushima, M, Maeda, T, Ishikawa, M, Fukaishi, M, Numata, K & Ohno, Y 1995, Sub-1 V supply voltage GaAs LSI technology based on 0.25 μm E/D-HJFETs (IS3Ts). in NEC Research and Development. 1 edn, vol. 36, pp. 147-156.
Hida H, Tokushima M, Maeda T, Ishikawa M, Fukaishi M, Numata K et al. Sub-1 V supply voltage GaAs LSI technology based on 0.25 μm E/D-HJFETs (IS3Ts). In NEC Research and Development. 1 ed. Vol. 36. 1995. p. 147-156
Hida, Hikaru ; Tokushima, Masatoshi ; Maeda, Tadashi ; Ishikawa, Masaoki ; Fukaishi, Muneo ; Numata, Keiichi ; Ohno, Yasuo. / Sub-1 V supply voltage GaAs LSI technology based on 0.25 μm E/D-HJFETs (IS3Ts). NEC Research and Development. Vol. 36 1. ed. 1995. pp. 147-156
@inbook{671ed516d842402592acfe53f6b29dfa,
title = "Sub-1 V supply voltage GaAs LSI technology based on 0.25 μm E/D-HJFETs (IS3Ts)",
abstract = "An advantage of lowering the supply voltage for low-power consumption LSIs without sacrificing speed is described, based on switching analysis of an E/D-FET DCFL (Enhancement/Depletion-mode FET Direct-Coupled FET Logic) inverter. This analysis takes into account the effect of current voltage characteristics in the non-saturation regime. New technology of fabricating 0.25 μm gate E/D GaAs Heterojunction (HJ) FET LSIs, which has been developed as a step towards the development of ultra-low supply voltage LSIs, is also described. This technology, which is based upon all dry-process techniques, includes the formation of a 0.25 μm gate opening by optical lithography, and inner SiO2 sidewalls. The fmax and gm max for a Y-shaped gate E-HJFET fabricated by this technology are 108 GHz and 520 mS/mm, respectively. Excellent performance is also obtained with DCFL ring oscillators using n-AlGaAs/i-InGaAs pseudomorphic E/D-HJFETs. These include 18 ps/gate unloaded delay and 109 ps/gate loaded delay (FI = FO = 3, L = 1 mm) with 0.15 mW/gate at 0.6 V, where inverters have a sufficient noise margin of more than 180 mV. In addition, 10 Gbps error-free operation of a selector switch is demonstrated with 9.4 mW at 0.6 V.",
author = "Hikaru Hida and Masatoshi Tokushima and Tadashi Maeda and Masaoki Ishikawa and Muneo Fukaishi and Keiichi Numata and Yasuo Ohno",
year = "1995",
month = "1",
language = "English",
volume = "36",
pages = "147--156",
booktitle = "NEC Research and Development",
edition = "1",

}

TY - CHAP

T1 - Sub-1 V supply voltage GaAs LSI technology based on 0.25 μm E/D-HJFETs (IS3Ts)

AU - Hida, Hikaru

AU - Tokushima, Masatoshi

AU - Maeda, Tadashi

AU - Ishikawa, Masaoki

AU - Fukaishi, Muneo

AU - Numata, Keiichi

AU - Ohno, Yasuo

PY - 1995/1

Y1 - 1995/1

N2 - An advantage of lowering the supply voltage for low-power consumption LSIs without sacrificing speed is described, based on switching analysis of an E/D-FET DCFL (Enhancement/Depletion-mode FET Direct-Coupled FET Logic) inverter. This analysis takes into account the effect of current voltage characteristics in the non-saturation regime. New technology of fabricating 0.25 μm gate E/D GaAs Heterojunction (HJ) FET LSIs, which has been developed as a step towards the development of ultra-low supply voltage LSIs, is also described. This technology, which is based upon all dry-process techniques, includes the formation of a 0.25 μm gate opening by optical lithography, and inner SiO2 sidewalls. The fmax and gm max for a Y-shaped gate E-HJFET fabricated by this technology are 108 GHz and 520 mS/mm, respectively. Excellent performance is also obtained with DCFL ring oscillators using n-AlGaAs/i-InGaAs pseudomorphic E/D-HJFETs. These include 18 ps/gate unloaded delay and 109 ps/gate loaded delay (FI = FO = 3, L = 1 mm) with 0.15 mW/gate at 0.6 V, where inverters have a sufficient noise margin of more than 180 mV. In addition, 10 Gbps error-free operation of a selector switch is demonstrated with 9.4 mW at 0.6 V.

AB - An advantage of lowering the supply voltage for low-power consumption LSIs without sacrificing speed is described, based on switching analysis of an E/D-FET DCFL (Enhancement/Depletion-mode FET Direct-Coupled FET Logic) inverter. This analysis takes into account the effect of current voltage characteristics in the non-saturation regime. New technology of fabricating 0.25 μm gate E/D GaAs Heterojunction (HJ) FET LSIs, which has been developed as a step towards the development of ultra-low supply voltage LSIs, is also described. This technology, which is based upon all dry-process techniques, includes the formation of a 0.25 μm gate opening by optical lithography, and inner SiO2 sidewalls. The fmax and gm max for a Y-shaped gate E-HJFET fabricated by this technology are 108 GHz and 520 mS/mm, respectively. Excellent performance is also obtained with DCFL ring oscillators using n-AlGaAs/i-InGaAs pseudomorphic E/D-HJFETs. These include 18 ps/gate unloaded delay and 109 ps/gate loaded delay (FI = FO = 3, L = 1 mm) with 0.15 mW/gate at 0.6 V, where inverters have a sufficient noise margin of more than 180 mV. In addition, 10 Gbps error-free operation of a selector switch is demonstrated with 9.4 mW at 0.6 V.

UR - http://www.scopus.com/inward/record.url?scp=0029237095&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029237095&partnerID=8YFLogxK

M3 - Chapter

AN - SCOPUS:0029237095

VL - 36

SP - 147

EP - 156

BT - NEC Research and Development

ER -