Submicrometer n+-Ge Gate AlGaAs/GaAs MISFET's

Makoto Hirano, Shuichi Fujita, Koichi Maezawa, Takashi Mizutani

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    5 Citations (Scopus)


    Submicrometer n+-Ge gate AlGaAs/GaAs M1SFET's have been developed by designing a fabrication process for the n+ - implanted region. The short-channel effect was sufficiently suppressed by lowering ion-implantation energy down to 50 keV to achieve a standard deviation of threshold voltage as small as 13 mV for 0.5-μm-gate FET's in a 2-in-diameter wafer. The source resistance was reduced by increasing the annealing temperature to 850°C to obtain a transconductance of 500 mS/mm for a 0.5-μm-gate FET. Even after annealing at such a high temperature, the quality of the channel layer was maintained at a sufficient level to realize a large cuttoff frequency of 70 GHz for a 0.4-μm-gate FET. A divide-by-four static frequency divider was also fabricated using the above-mentioned fabrication technology. Successful operation at 16 GHz at 300 K was obtained with a divider employing 0.9-μm-gate FET's at a low power dissipation of 36 mW per T-flip-flop.

    Original languageEnglish
    Pages (from-to)2217-2222
    Number of pages6
    JournalIEEE Transactions on Electron Devices
    Issue number10
    Publication statusPublished - 1989 Oct

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering


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