A novel design technique which combines a Variable Supply-voltage scheme and a Clustered Voltage Scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay, area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit, performance compared to a conventional CMOS design.
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|Publication status||Published - 1998 Jan 1|
|Event||Proceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA|
Duration: 1998 May 11 → 1998 May 14
ASJC Scopus subject areas
- Electrical and Electronic Engineering