Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

Mototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda

Research output: Contribution to journalConference articlepeer-review

80 Citations (Scopus)

Abstract

A novel design technique which combines a Variable Supply-voltage scheme and a Clustered Voltage Scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay, area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit, performance compared to a conventional CMOS design.

Original languageEnglish
Pages (from-to)495-498
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 1998 Jan 1
Externally publishedYes
EventProceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: 1998 May 111998 May 14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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