Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

Mototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

78 Citations (Scopus)

Abstract

A novel design technique which combines a Variable Supply-voltage scheme and a Clustered Voltage Scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay, area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit, performance compared to a conventional CMOS design.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
Editors Anon
PublisherIEEE
Pages495-498
Number of pages4
Publication statusPublished - 1998
Externally publishedYes
EventProceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: 1998 May 111998 May 14

Other

OtherProceedings of the 1998 IEEE Custom Integrated Circuits Conference
CitySanta Clara, CA, USA
Period98/5/1198/5/14

Fingerprint

Electric potential
Flip flop circuits
Energy dissipation
Networks (circuits)
Voltage scaling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Hamada, M., Takahashi, M., Arakida, H., Chiba, A., Terazawa, T., Ishikawa, T., ... Kuroda, T. (1998). Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. In Anon (Ed.), Proceedings of the Custom Integrated Circuits Conference (pp. 495-498). IEEE.

Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. / Hamada, Mototsugu; Takahashi, Masafumi; Arakida, Hideho; Chiba, Akihiko; Terazawa, Toshihiro; Ishikawa, Takashi; Kanazawa, Masahiro; Igarashi, Mutsunori; Usami, Kimiyoshi; Kuroda, Tadahiro.

Proceedings of the Custom Integrated Circuits Conference. ed. / Anon. IEEE, 1998. p. 495-498.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hamada, M, Takahashi, M, Arakida, H, Chiba, A, Terazawa, T, Ishikawa, T, Kanazawa, M, Igarashi, M, Usami, K & Kuroda, T 1998, Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. in Anon (ed.), Proceedings of the Custom Integrated Circuits Conference. IEEE, pp. 495-498, Proceedings of the 1998 IEEE Custom Integrated Circuits Conference, Santa Clara, CA, USA, 98/5/11.
Hamada M, Takahashi M, Arakida H, Chiba A, Terazawa T, Ishikawa T et al. Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. In Anon, editor, Proceedings of the Custom Integrated Circuits Conference. IEEE. 1998. p. 495-498
Hamada, Mototsugu ; Takahashi, Masafumi ; Arakida, Hideho ; Chiba, Akihiko ; Terazawa, Toshihiro ; Ishikawa, Takashi ; Kanazawa, Masahiro ; Igarashi, Mutsunori ; Usami, Kimiyoshi ; Kuroda, Tadahiro. / Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. Proceedings of the Custom Integrated Circuits Conference. editor / Anon. IEEE, 1998. pp. 495-498
@inproceedings{e8bb84c79bdc4bdab5136bdeb1d2defa,
title = "Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme",
abstract = "A novel design technique which combines a Variable Supply-voltage scheme and a Clustered Voltage Scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay, area penalties significantly. Application of this technique to an MPEG4 video codec saves 55{\%} of the power dissipation without degrading circuit, performance compared to a conventional CMOS design.",
author = "Mototsugu Hamada and Masafumi Takahashi and Hideho Arakida and Akihiko Chiba and Toshihiro Terazawa and Takashi Ishikawa and Masahiro Kanazawa and Mutsunori Igarashi and Kimiyoshi Usami and Tadahiro Kuroda",
year = "1998",
language = "English",
pages = "495--498",
editor = "Anon",
booktitle = "Proceedings of the Custom Integrated Circuits Conference",
publisher = "IEEE",

}

TY - GEN

T1 - Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

AU - Hamada, Mototsugu

AU - Takahashi, Masafumi

AU - Arakida, Hideho

AU - Chiba, Akihiko

AU - Terazawa, Toshihiro

AU - Ishikawa, Takashi

AU - Kanazawa, Masahiro

AU - Igarashi, Mutsunori

AU - Usami, Kimiyoshi

AU - Kuroda, Tadahiro

PY - 1998

Y1 - 1998

N2 - A novel design technique which combines a Variable Supply-voltage scheme and a Clustered Voltage Scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay, area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit, performance compared to a conventional CMOS design.

AB - A novel design technique which combines a Variable Supply-voltage scheme and a Clustered Voltage Scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay, area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit, performance compared to a conventional CMOS design.

UR - http://www.scopus.com/inward/record.url?scp=0031634512&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031634512&partnerID=8YFLogxK

M3 - Conference contribution

SP - 495

EP - 498

BT - Proceedings of the Custom Integrated Circuits Conference

A2 - Anon, null

PB - IEEE

ER -