Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Weihan Wang, Yuya Ohta, Yoshifumi Ishii, Kimiyoshi Usami, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

High-speed power gating (PG) techniques are useful for reducing leakage power of functional units in a CPU core. This paper analyzes trade off of functional units in a MIPS R3000 based processor with three fine-grained PG methods: the cell-based, row-based and ring-based. Compared with the cell-based PG technique, which was used in our previous work - Geyser-1 processor, the row-based and ring-based PG technique achieved much smaller area and less implemental cost with a certain additional delay to wake-up latency. The simulation results with benchmark programs show that all three methods can reduce leakage power by 28∼54% at 25C.

Original languageEnglish
Title of host publicationSymposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV
DOIs
Publication statusPublished - 2012 Jul 25
Event15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV - Yokohama, Japan
Duration: 2012 Apr 182012 Apr 20

Publication series

NameSymposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV

Conference

Conference15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV
CountryJapan
CityYokohama
Period12/4/1812/4/20

Keywords

  • Leakage Power and Processor
  • Power Gating

ASJC Scopus subject areas

  • Computer Networks and Communications

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    Wang, W., Ohta, Y., Ishii, Y., Usami, K., & Amano, H. (2012). Trade-off analysis of fine-grained power gating methods for functional units in a CPU. In Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV [6216587] (Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV). https://doi.org/10.1109/COOLChips.2012.6216587