Two-dimensional analysis of field-plate effects on surface-state-related current transients and power slump in GaAs FETs

Kazushige Horio, Toshiya Tanaka, Keiichi Itagaki, Atsushi Nakajima

Research output: Contribution to journalArticle

24 Citations (Scopus)


In this paper, we carry out a 2-D transient analysis of field-plate GaAs metal-semiconductor field-effect transistors (FETs) by taking surface states into account. Quasi-pulsed currentvoltage curves are derived from the transient characteristics. We show that drain lag and current slump (power slump) due to surface states are reduced by introducing a field plate because the fixed potential at the field plate mitigates the trapping effects of the surface states. The dependence of lag and current slump on the field-plate length and the SiO2 passivation layer thickness is also studied. We show that it is possible to reduce the current slump and maintain the high-frequency performance of GaAs FETs at optimum values of the field-plate length and the SiO2 layer thickness.

Original languageEnglish
Article number5667052
Pages (from-to)698-703
Number of pages6
JournalIEEE Transactions on Electron Devices
Issue number3
Publication statusPublished - 2011 Mar 1



  • Drain lag
  • GaAs field-effect transistor (FET)
  • gate lag
  • power slump
  • surface state

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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