Two-dimensional analysis of gate-lag phenomena in recessed-gate GaAs MESFETs

Kazushige Horio, T. Yamada

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Effects of surface states on turn-on characteristics of recessed-gate GaAs MESFETs are studied by two-dimensional simulation. It is found that the recess depth dr is deep and the distance between the gate and the recess edge Lr is set to be very narrow, the gate-lag (slow current transient) extinguishes for a case with surface states considered on horizontal planes only. However, in a realistic case with surface states included on both horizontal and vertical planes, the gate-lag is not eliminated even if dr is made rather deep. This is attributed to the fact that when the deep-acceptor-like surface state acts as a hole trap, the thickness of surface depletion layer can change much by the applied gate bias. To eliminate the gate-lag, the deep acceptor should be made electron-trap type. This can be realized by reducing the surface state density.

Original languageEnglish
Title of host publicationWorkshop on High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO
Editors Anon
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages7-12
Number of pages6
Publication statusPublished - 1997
EventProceedings of the 1997 Workshop on High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO - London, UK
Duration: 1997 Nov 241997 Nov 25

Other

OtherProceedings of the 1997 Workshop on High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO
CityLondon, UK
Period97/11/2497/11/25

Fingerprint

Surface states
Hole traps
Electron traps

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Horio, K., & Yamada, T. (1997). Two-dimensional analysis of gate-lag phenomena in recessed-gate GaAs MESFETs. In Anon (Ed.), Workshop on High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO (pp. 7-12). Piscataway, NJ, United States: IEEE.

Two-dimensional analysis of gate-lag phenomena in recessed-gate GaAs MESFETs. / Horio, Kazushige; Yamada, T.

Workshop on High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO. ed. / Anon. Piscataway, NJ, United States : IEEE, 1997. p. 7-12.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Horio, K & Yamada, T 1997, Two-dimensional analysis of gate-lag phenomena in recessed-gate GaAs MESFETs. in Anon (ed.), Workshop on High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO. IEEE, Piscataway, NJ, United States, pp. 7-12, Proceedings of the 1997 Workshop on High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO, London, UK, 97/11/24.
Horio K, Yamada T. Two-dimensional analysis of gate-lag phenomena in recessed-gate GaAs MESFETs. In Anon, editor, Workshop on High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO. Piscataway, NJ, United States: IEEE. 1997. p. 7-12
Horio, Kazushige ; Yamada, T. / Two-dimensional analysis of gate-lag phenomena in recessed-gate GaAs MESFETs. Workshop on High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO. editor / Anon. Piscataway, NJ, United States : IEEE, 1997. pp. 7-12
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