Two-dimensional analysis of surface-state effects on turn-on characteristics in GaAs MESFET's

Kazushige Horio, Tomiko Yamada

Research output: Contribution to journalArticle

57 Citations (Scopus)

Abstract

Surface-state effects on gate-lag or slow current transient in GaAs MESFET's are studied by two-dimensional (2-D) simulation. It is shown that the gate-lag becomes remarkable when the deep-acceptor surface state acts as a hole trap. To suppress it, the deep acceptor should be made electron-trap-like, which can be realized by reducing the surface-state density. Device structures expected to have less gate-lag, such as a self-aligned structure with n+ source and drain regions and a recessed-gate structure are also analyzed. An analysis of the possible complete elimination of gate-lag in these structures is given.

Original languageEnglish
Pages (from-to)648-655
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume46
Issue number4
DOIs
Publication statusPublished - 1999

Fingerprint

dimensional analysis
Surface states
field effect transistors
time lag
Hole traps
Electron traps
traps
elimination
gallium arsenide
electrons
simulation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)

Cite this

Two-dimensional analysis of surface-state effects on turn-on characteristics in GaAs MESFET's. / Horio, Kazushige; Yamada, Tomiko.

In: IEEE Transactions on Electron Devices, Vol. 46, No. 4, 1999, p. 648-655.

Research output: Contribution to journalArticle

@article{5a38967325f1469b9b1f63cb6e063ecb,
title = "Two-dimensional analysis of surface-state effects on turn-on characteristics in GaAs MESFET's",
abstract = "Surface-state effects on gate-lag or slow current transient in GaAs MESFET's are studied by two-dimensional (2-D) simulation. It is shown that the gate-lag becomes remarkable when the deep-acceptor surface state acts as a hole trap. To suppress it, the deep acceptor should be made electron-trap-like, which can be realized by reducing the surface-state density. Device structures expected to have less gate-lag, such as a self-aligned structure with n+ source and drain regions and a recessed-gate structure are also analyzed. An analysis of the possible complete elimination of gate-lag in these structures is given.",
author = "Kazushige Horio and Tomiko Yamada",
year = "1999",
doi = "10.1109/16.753696",
language = "English",
volume = "46",
pages = "648--655",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

TY - JOUR

T1 - Two-dimensional analysis of surface-state effects on turn-on characteristics in GaAs MESFET's

AU - Horio, Kazushige

AU - Yamada, Tomiko

PY - 1999

Y1 - 1999

N2 - Surface-state effects on gate-lag or slow current transient in GaAs MESFET's are studied by two-dimensional (2-D) simulation. It is shown that the gate-lag becomes remarkable when the deep-acceptor surface state acts as a hole trap. To suppress it, the deep acceptor should be made electron-trap-like, which can be realized by reducing the surface-state density. Device structures expected to have less gate-lag, such as a self-aligned structure with n+ source and drain regions and a recessed-gate structure are also analyzed. An analysis of the possible complete elimination of gate-lag in these structures is given.

AB - Surface-state effects on gate-lag or slow current transient in GaAs MESFET's are studied by two-dimensional (2-D) simulation. It is shown that the gate-lag becomes remarkable when the deep-acceptor surface state acts as a hole trap. To suppress it, the deep acceptor should be made electron-trap-like, which can be realized by reducing the surface-state density. Device structures expected to have less gate-lag, such as a self-aligned structure with n+ source and drain regions and a recessed-gate structure are also analyzed. An analysis of the possible complete elimination of gate-lag in these structures is given.

UR - http://www.scopus.com/inward/record.url?scp=0032662051&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032662051&partnerID=8YFLogxK

U2 - 10.1109/16.753696

DO - 10.1109/16.753696

M3 - Article

VL - 46

SP - 648

EP - 655

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 4

ER -