Ultra fine-grained run-time power gating of on-chip routers for CMPs

Hiroki Matsutani, Michihiro Koibuchi, Daisuk Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

42 Citations (Scopus)

Abstract

This paper proposes an ultra fine-grained run-time power gating of on-chip router, in which power supply to each router component (e.g., VC queue, crossbar MUX, and output latch) can be individually controlled in response to the applied workload. As only the router components which are just transferring a packet are activated, the leakage power of the on-chip network can be reduced to the near-optimal level. However, a certain amount of wakeup latency is required to activate the sleeping components, and the application performance will be degraded. In this paper, we estimate the wakeup latency for each component based on circuit simulations using a 65nm process. Then we propose four early wakeup methods to overcome the wakeup latency. The proposed router with the early wakeup methods is evaluated in terms of the application performance, area, and leakage power. As a result, it reduces the leakage power by 78.9%, at the expense of the 4.3% area and 4.0% performance when we assume a 1GHz operation.

Original languageEnglish
Title of host publicationNOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip
Pages61-68
Number of pages8
DOIs
Publication statusPublished - 2010
Event4th ACM/IEEE International Symposium on Networks on Chip, NOCS 2010 - Grenoble
Duration: 2010 May 32010 May 6

Other

Other4th ACM/IEEE International Symposium on Networks on Chip, NOCS 2010
CityGrenoble
Period10/5/310/5/6

Fingerprint

Routers
Circuit simulation

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H., & Amano, H. (2010). Ultra fine-grained run-time power gating of on-chip routers for CMPs. In NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip (pp. 61-68). [5507560] https://doi.org/10.1109/NOCS.2010.16

Ultra fine-grained run-time power gating of on-chip routers for CMPs. / Matsutani, Hiroki; Koibuchi, Michihiro; Ikebuchi, Daisuk; Usami, Kimiyoshi; Nakamura, Hiroshi; Amano, Hideharu.

NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. 2010. p. 61-68 5507560.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Matsutani, H, Koibuchi, M, Ikebuchi, D, Usami, K, Nakamura, H & Amano, H 2010, Ultra fine-grained run-time power gating of on-chip routers for CMPs. in NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip., 5507560, pp. 61-68, 4th ACM/IEEE International Symposium on Networks on Chip, NOCS 2010, Grenoble, 10/5/3. https://doi.org/10.1109/NOCS.2010.16
Matsutani H, Koibuchi M, Ikebuchi D, Usami K, Nakamura H, Amano H. Ultra fine-grained run-time power gating of on-chip routers for CMPs. In NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. 2010. p. 61-68. 5507560 https://doi.org/10.1109/NOCS.2010.16
Matsutani, Hiroki ; Koibuchi, Michihiro ; Ikebuchi, Daisuk ; Usami, Kimiyoshi ; Nakamura, Hiroshi ; Amano, Hideharu. / Ultra fine-grained run-time power gating of on-chip routers for CMPs. NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. 2010. pp. 61-68
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