Ultra-high-speed and universal-coding-rate Viterbi decoder VLSIC-SNUFEC VLSI

Katsuhiko Kawazoe, Shunji Honda, Shuji Kubota, Shuzo Kato

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

An Ultra-high-speed (higher than 60Mbps) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-μm semi-custom CMOS LSIC technology. To reduce the power consumption of the one-chip high-coding-rate Viterbi decoder, a newly developed universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been employed. In addition, a new maximum-likelihood-decision (MLD) circuit of the SST Viterbi decoder has been developed to reduce the path memory length without coding-gain degradation. The developed Viterbi decoder VLSIC achieves a maximum data rate of 60Mbps with a power consumption of 2.5W and achieves near theoretical net coding-gain performance for various coding rates.

Original languageEnglish
Title of host publicationIEEE International Conference on Communications
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Pages1434-1438
Number of pages5
ISBN (Print)0780309510
Publication statusPublished - 1993
Externally publishedYes
EventProceedings of the IEEE International Conference on Communications '93 - Geneva, Switz
Duration: 1993 May 231993 May 26

Other

OtherProceedings of the IEEE International Conference on Communications '93
CityGeneva, Switz
Period93/5/2393/5/26

Fingerprint

Electric power utilization
Data storage equipment
Forward error correction
Maximum likelihood
Decoding
Degradation
Networks (circuits)

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Kawazoe, K., Honda, S., Kubota, S., & Kato, S. (1993). Ultra-high-speed and universal-coding-rate Viterbi decoder VLSIC-SNUFEC VLSI. In IEEE International Conference on Communications (pp. 1434-1438). Piscataway, NJ, United States: Publ by IEEE.

Ultra-high-speed and universal-coding-rate Viterbi decoder VLSIC-SNUFEC VLSI. / Kawazoe, Katsuhiko; Honda, Shunji; Kubota, Shuji; Kato, Shuzo.

IEEE International Conference on Communications. Piscataway, NJ, United States : Publ by IEEE, 1993. p. 1434-1438.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kawazoe, K, Honda, S, Kubota, S & Kato, S 1993, Ultra-high-speed and universal-coding-rate Viterbi decoder VLSIC-SNUFEC VLSI. in IEEE International Conference on Communications. Publ by IEEE, Piscataway, NJ, United States, pp. 1434-1438, Proceedings of the IEEE International Conference on Communications '93, Geneva, Switz, 93/5/23.
Kawazoe K, Honda S, Kubota S, Kato S. Ultra-high-speed and universal-coding-rate Viterbi decoder VLSIC-SNUFEC VLSI. In IEEE International Conference on Communications. Piscataway, NJ, United States: Publ by IEEE. 1993. p. 1434-1438
Kawazoe, Katsuhiko ; Honda, Shunji ; Kubota, Shuji ; Kato, Shuzo. / Ultra-high-speed and universal-coding-rate Viterbi decoder VLSIC-SNUFEC VLSI. IEEE International Conference on Communications. Piscataway, NJ, United States : Publ by IEEE, 1993. pp. 1434-1438
@inproceedings{00dc17a4ea3b4343969005c9663c214a,
title = "Ultra-high-speed and universal-coding-rate Viterbi decoder VLSIC-SNUFEC VLSI",
abstract = "An Ultra-high-speed (higher than 60Mbps) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-μm semi-custom CMOS LSIC technology. To reduce the power consumption of the one-chip high-coding-rate Viterbi decoder, a newly developed universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been employed. In addition, a new maximum-likelihood-decision (MLD) circuit of the SST Viterbi decoder has been developed to reduce the path memory length without coding-gain degradation. The developed Viterbi decoder VLSIC achieves a maximum data rate of 60Mbps with a power consumption of 2.5W and achieves near theoretical net coding-gain performance for various coding rates.",
author = "Katsuhiko Kawazoe and Shunji Honda and Shuji Kubota and Shuzo Kato",
year = "1993",
language = "English",
isbn = "0780309510",
pages = "1434--1438",
booktitle = "IEEE International Conference on Communications",
publisher = "Publ by IEEE",

}

TY - GEN

T1 - Ultra-high-speed and universal-coding-rate Viterbi decoder VLSIC-SNUFEC VLSI

AU - Kawazoe, Katsuhiko

AU - Honda, Shunji

AU - Kubota, Shuji

AU - Kato, Shuzo

PY - 1993

Y1 - 1993

N2 - An Ultra-high-speed (higher than 60Mbps) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-μm semi-custom CMOS LSIC technology. To reduce the power consumption of the one-chip high-coding-rate Viterbi decoder, a newly developed universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been employed. In addition, a new maximum-likelihood-decision (MLD) circuit of the SST Viterbi decoder has been developed to reduce the path memory length without coding-gain degradation. The developed Viterbi decoder VLSIC achieves a maximum data rate of 60Mbps with a power consumption of 2.5W and achieves near theoretical net coding-gain performance for various coding rates.

AB - An Ultra-high-speed (higher than 60Mbps) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-μm semi-custom CMOS LSIC technology. To reduce the power consumption of the one-chip high-coding-rate Viterbi decoder, a newly developed universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been employed. In addition, a new maximum-likelihood-decision (MLD) circuit of the SST Viterbi decoder has been developed to reduce the path memory length without coding-gain degradation. The developed Viterbi decoder VLSIC achieves a maximum data rate of 60Mbps with a power consumption of 2.5W and achieves near theoretical net coding-gain performance for various coding rates.

UR - http://www.scopus.com/inward/record.url?scp=0027294294&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027294294&partnerID=8YFLogxK

M3 - Conference contribution

SN - 0780309510

SP - 1434

EP - 1438

BT - IEEE International Conference on Communications

PB - Publ by IEEE

CY - Piscataway, NJ, United States

ER -