Ultra-high-speed and universal-coding-rate Viterbi decoder VLSIC - SNUFEC VLSI

Katsuhiko Kawazoe, Shunji Honda, Shuji Kubota, Shuzo Kato

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-μm semi-custom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decoder VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.

Original languageEnglish
Pages (from-to)1888-1894
Number of pages7
JournalIEICE Transactions on Electronics
VolumeE77-C
Issue number12
Publication statusPublished - 1994 Dec 1

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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