Ultra-low-power-consumption heterojunction FET 8:1 MUX/1:8 DEMUX for 2.4-GBPS optical-fiber communication systems

Keiichi Numata, Masahiro Fujii, Tadashi Maeda, Masatoshi Tokushima, Shigeki Wada, Muneo Fukaishi, Masaoki Ishikawa

Research output: Contribution to conferencePaper

4 Citations (Scopus)

Abstract

A gallium arsenide 8:1 multiplexer (MUX) and a 1:8 demultiplexer (DEMUX) for 2.4 Gbps optical communication systems have been developed. These LSIs employ a tree-type architecture using 2:1 MUXs/1:2 DEMUXs that is suitable for high-speed and low power operation but requires precise control of clock timing. To ensure timing margins, a new timing generator and clock buffer circuit have been developed. These LSIs operate at over 2.4 Gbps with 150-mW of power consumption at a supply voltage of 0.7 V.

Original languageEnglish
Pages39-42
Number of pages4
Publication statusPublished - 1995 Dec 1
EventProceedings of the 17th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - San Diego, CA, USA
Duration: 1995 Oct 291995 Nov 1

Other

OtherProceedings of the 17th Annual IEEE Gallium Arsenide Integrated Circuit Symposium
CitySan Diego, CA, USA
Period95/10/2995/11/1

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Numata, K., Fujii, M., Maeda, T., Tokushima, M., Wada, S., Fukaishi, M., & Ishikawa, M. (1995). Ultra-low-power-consumption heterojunction FET 8:1 MUX/1:8 DEMUX for 2.4-GBPS optical-fiber communication systems. 39-42. Paper presented at Proceedings of the 17th Annual IEEE Gallium Arsenide Integrated Circuit Symposium, San Diego, CA, USA, .