Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating

Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper describes a new approach to reduce the ground bounce (GB) while keeping the wakeup time short for fine-grain power gating. We propose a novel algorithm to synthesize an optimal unbalanced buffer tree (UBT) that turns on parallel power switches with slight time differences. We have applied our algorithm to function units of a 32-bit microprocessor. Experimental results have revealed that our UBT gives better solution than the conventional daisy-chain approach in the space of wakeup time and GB. For example, in the ALU, our UBT suppressed the maximum GB voltage to 16mV which is 24% smaller than that of the parallel daisy chain, while keeping the wakeup time 0.6ns. In the 32b×32b multiplier, our UBT suppressed GB by 32% lower than the daisy chain but still kept the wakeup time 0.7ns. The microprocessor test chip with our UBT technique is successfully under operation.

Original languageEnglish
Title of host publication2014 International Symposium on System-on-Chip, SoC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479968909
DOIs
Publication statusPublished - 2014 Dec 2
Event2014 16th International Symposium on System-on-Chip, SoC 2014 - Tampere
Duration: 2014 Oct 282014 Oct 29

Other

Other2014 16th International Symposium on System-on-Chip, SoC 2014
CityTampere
Period14/10/2814/10/29

Fingerprint

Microprocessor chips
Switches
Electric potential

Keywords

  • ground bounce
  • low power
  • power gating

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Usami, K., Miyauchi, M., Kudo, M., Takagi, K., Amano, H., Namiki, M., ... Nakamura, H. (2014). Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. In 2014 International Symposium on System-on-Chip, SoC 2014 [6972438] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSOC.2014.6972438

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. / Usami, Kimiyoshi; Miyauchi, Makoto; Kudo, Masaru; Takagi, Kazumitsu; Amano, Hideharu; Namiki, Mitaro; Kondo, Masaaki; Nakamura, Hiroshi.

2014 International Symposium on System-on-Chip, SoC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6972438.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Usami, K, Miyauchi, M, Kudo, M, Takagi, K, Amano, H, Namiki, M, Kondo, M & Nakamura, H 2014, Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. in 2014 International Symposium on System-on-Chip, SoC 2014., 6972438, Institute of Electrical and Electronics Engineers Inc., 2014 16th International Symposium on System-on-Chip, SoC 2014, Tampere, 14/10/28. https://doi.org/10.1109/ISSOC.2014.6972438
Usami K, Miyauchi M, Kudo M, Takagi K, Amano H, Namiki M et al. Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. In 2014 International Symposium on System-on-Chip, SoC 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6972438 https://doi.org/10.1109/ISSOC.2014.6972438
Usami, Kimiyoshi ; Miyauchi, Makoto ; Kudo, Masaru ; Takagi, Kazumitsu ; Amano, Hideharu ; Namiki, Mitaro ; Kondo, Masaaki ; Nakamura, Hiroshi. / Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. 2014 International Symposium on System-on-Chip, SoC 2014. Institute of Electrical and Electronics Engineers Inc., 2014.
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