Abstract
A very low power consumption Viterbi decoder LSIC has been developed by using a low supply voltage 0.8μm CMOS master slice process technology. By employing the scarce state transition (SST) scheme, this LSIC achieves a drastic reduction in power consumption below 600μW at a supply voltage of IV when the data rate is 1152kbit/s and the bit error rate is less than 10-3. This excellent performance has paved the way to employing the strong forward error correction and low power consumption portable terminals for personal communications, mobile multimedia communications, and digital and audio broadcasting.
| Original language | English |
|---|---|
| Pages (from-to) | 637-639 |
| Number of pages | 3 |
| Journal | Electronics Letters |
| Volume | 30 |
| Issue number | 8 |
| DOIs | |
| Publication status | Published - 1994 Jan 1 |
| Externally published | Yes |
Fingerprint
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Very low power consumption Viterbi decoder LSIC employing the SST (scarce state transition) scheme for multimedia mobile communications. / Seki, K.; Kubota, Shuji; Mizoguchi, M.; Kato, S.
In: Electronics Letters, Vol. 30, No. 8, 01.01.1994, p. 637-639.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Very low power consumption Viterbi decoder LSIC employing the SST (scarce state transition) scheme for multimedia mobile communications
AU - Seki, K.
AU - Kubota, Shuji
AU - Mizoguchi, M.
AU - Kato, S.
PY - 1994/1/1
Y1 - 1994/1/1
N2 - A very low power consumption Viterbi decoder LSIC has been developed by using a low supply voltage 0.8μm CMOS master slice process technology. By employing the scarce state transition (SST) scheme, this LSIC achieves a drastic reduction in power consumption below 600μW at a supply voltage of IV when the data rate is 1152kbit/s and the bit error rate is less than 10-3. This excellent performance has paved the way to employing the strong forward error correction and low power consumption portable terminals for personal communications, mobile multimedia communications, and digital and audio broadcasting.
AB - A very low power consumption Viterbi decoder LSIC has been developed by using a low supply voltage 0.8μm CMOS master slice process technology. By employing the scarce state transition (SST) scheme, this LSIC achieves a drastic reduction in power consumption below 600μW at a supply voltage of IV when the data rate is 1152kbit/s and the bit error rate is less than 10-3. This excellent performance has paved the way to employing the strong forward error correction and low power consumption portable terminals for personal communications, mobile multimedia communications, and digital and audio broadcasting.
UR - http://www.scopus.com/inward/record.url?scp=0028405923&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0028405923&partnerID=8YFLogxK
U2 - 10.1049/el:19940460
DO - 10.1049/el:19940460
M3 - Article
AN - SCOPUS:0028405923
VL - 30
SP - 637
EP - 639
JO - Electronics Letters
JF - Electronics Letters
SN - 0013-5194
IS - 8
ER -