A very low power consumption Viterbi decoder LSIC has been developed by using a low supply voltage 0.8 μm CMOS masterslice process technology. By employing the scarce state transition (SST) scheme, this LSIC achieves a drastic reduction in power consumption below 600 μW at a supply voltage of 1V when the data rate is 1152 kbit/s and the bit error rate is less than 10-3. This excellent performance has paved the way to employing the strong forward error correction and low power consumption portable terminals for personal communications, mobile multimedia communications, and digital and audio broadcasting.
|Number of pages||3|
|Publication status||Published - 1994 Jan 1|
- Integrated circuits
- Large scale integration
- Viterbi decoding
ASJC Scopus subject areas
- Electrical and Electronic Engineering