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研究成果 1987 2019

  • 1603 引用
  • 20 h指数
  • 68 Conference contribution
  • 36 Article
  • 1 Chapter
1987

DESIGN METHODOLOGY OF STANDARD CELL LAYOUT AND PLA.

Usami, K., Ishii, A., Horie, A. & Iwamura, J., 1987, Proceedings of the Custom Integrated Circuits Conference. IEEE, p. 379-384 6 p.

研究成果: Conference contribution

Fans
Macros
1988
4 引用 (Scopus)

Design of a 32bit microprocessor, TX1

Tokumaru, T., Masuda, E., Hori, C., Usami, K., Miyata, M. & Iwamura, J., 1988, 1988 Symp VLSI Circuits Dig Tech Pap. Anon (版). p. 33-34 2 p.

研究成果: Conference contribution

Microprocessor chips
Routers
Clocks
Automation
Logic Synthesis
1989
1 引用 (Scopus)

Design of a 32-bit microprocessor, TX1

Tokumaru, T., Masuda, E., Usami, K., Usami, K., Miyata, M. & Iwamura, J., 1989 8, : : IEEE Journal of Solid-State Circuits. 24, 4, p. 938-944 7 p.

研究成果: Article

Microprocessor chips
Design for testability
Clocks
Transistors
Metals
1 引用 (Scopus)

Optimized design method for full-custom microprocessors

Usami, K. & Iwamura, J., 1989 5, Proceedings of the Custom Integrated Circuits Conference. Anon (版). Publ by IEEE

研究成果: Conference contribution

Microprocessor chips
Transistors
1990
1 引用 (Scopus)

Datapath generator based on gate-level symbolic layout

Matsumoto, N., Watanabe, Y., Usami, K., Sugeno, Y., Hatada, H. & Mori, S., 1990, 27th ACM/IEEE Design Automation Conference. Proceedings 1990. Piscataway, NJ, United States: Publ by IEEE, p. 388-393 6 p.

研究成果: Conference contribution

Masks
Transistors
1 引用 (Scopus)

Hierarchical symbolic design methodology for large-scale datapaths

Usami, K., Sugeno, Y., Matsumoto, N. & Mori, S., 1990, Proceedings of the Custom Integrated Circuits Conference. Publ by IEEE

研究成果: Conference contribution

Electric wiring
Masks
Transistors
Compaction
1991

Hierarchical symbolic design methodology for large-scale data paths

Usami, K., Sugeno, Y., Matsumoto, N. & Mori, S., 1991 3, : : IEEE Journal of Solid-State Circuits. 26, 3, p. 381-385 5 p.

研究成果: Article

Turnaround time
Adders
Microprocessor chips
Masks
Transistors
1995
322 引用 (Scopus)

Clustered voltage scaling technique for low-power design

Usami, K. & Horowitz, M., 1995, Proceedings of the International Symposium on Low Power Design. New York, NY, United States: ACM, p. 3-8 6 p.

研究成果: Conference contribution

Networks (circuits)
Electric potential
Microprocessor chips
Voltage scaling
1996
24 引用 (Scopus)

Low-power design technique for ASICs by partially reducing supply voltage

Usami, K., Ishikawa, T., Kanazawa, M. & Kotani, H., 1996, Proceedings of the Annual IEEE International ASIC Conference and Exhibit. Meindl, J. D., Mukund, P. R., Gabara, T. & Sridhar, R. (版). p. 301-304 4 p.

研究成果: Conference contribution

Application specific integrated circuits
Electric potential
Capacitance
Wire
Degradation
1997
22 引用 (Scopus)

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Usami, K., Nogami, K., Igarashi, M., Minami, F., Kawasaki, Y., Ishikawa, T., Kanazawa, M., Aoki, T., Takano, M., Mizuno, C., Ichida, M., Sonoda, S., Takahashi, M. & Hatanaka, N., 1997, Proceedings of the Custom Integrated Circuits Conference. IEEE, p. 131-134 4 p.

研究成果: Conference contribution

Electric potential
51 引用 (Scopus)

Low-power design method using multiple supply voltages

Igarashi, M., Usami, K., Nogami, K., Minami, F., Kawasaki, Y., Aoki, T., Takano, M., Mizuno, C., Lshikawa, T., Kanazawa, M., Sonoda, S., Ichida, M. & Hatanaka, N., 1997, International Symposium on Low Power Electronics and Design, Digest of Technical Papers. Piscataway, NJ, United States: IEEE, p. 36-41 6 p.

研究成果: Conference contribution

Electric potential
Electric wiring
Logic circuits
Electric power utilization
Voltage scaling
1998
13 引用 (Scopus)

60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Tsuboi, Y., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Momose, H. & Usami, K., 1998, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Anon (版). IEEE, p. 36-37 2 p.

研究成果: Conference contribution

Energy dissipation
Electric potential
Motion pictures
Networks (circuits)
Threshold voltage
72 引用 (Scopus)

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Usami, K., Igarashi, M., Ishikawa, T., Kanazawa, M., Kuroda, T. & Furuyama, T., 1998 11, : : IEEE Journal of Solid-State Circuits. 33, 11, p. 1772-1778 7 p.

研究成果: Article

Energy dissipation
Static random access storage
Electric potential
Computer hardware
Decoding
191 引用 (Scopus)

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Usami, K., Igarashi, M., Minami, F., Ishikawa, T., Kanazawa, M., Ichida, M. & Nogami, K., 1998 3, : : IEEE Journal of Solid-State Circuits. 33, 3, p. 463-471 9 p.

研究成果: Article

Electric potential
Clocks
12 引用 (Scopus)

Clock-gating method for low-power LSI design

Kitahara, T., Minami, F., Ueda, T., Usami, K., Nishio, S., Murakata, M. & Mitsuhashi, T., 1998, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE, p. 307-312 6 p.

研究成果: Chapter

Clocks
Networks (circuits)
29 引用 (Scopus)

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

Usami, K., Igarashi, M., Ishikawa, T., Kanazawa, M., Takahashi, M., Hamada, M., Arakida, H., Terazawa, T. & Kuroda, T., 1998, Proceedings - Design Automation Conference. IEEE, p. 483-488 6 p.

研究成果: Conference contribution

Turnaround time
Electric potential
Voltage scaling
78 引用 (Scopus)

Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

Hamada, M., Takahashi, M., Arakida, H., Chiba, A., Terazawa, T., Ishikawa, T., Kanazawa, M., Igarashi, M., Usami, K. & Kuroda, T., 1998, Proceedings of the Custom Integrated Circuits Conference. Anon (版). IEEE, p. 495-498 4 p.

研究成果: Conference contribution

Electric potential
Flip flop circuits
Energy dissipation
Networks (circuits)
Voltage scaling
2000
66 引用 (Scopus)

Function-level power estimation methodology for microprocessors

Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2000, Proceedings - Design Automation Conference. IEEE, p. 810-813 4 p.

研究成果: Conference contribution

Microprocessor chips
Embedded software
Energy dissipation
Energy utilization
Simulators
30 引用 (Scopus)

Low-power design methodology and applications utilizing dual supply voltages

Usami, K. & Igarashi, M., 2000, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 123-128 6 p.

研究成果: Conference contribution

Flip flop circuits
Electric potential
Networks (circuits)
6 引用 (Scopus)

Low-power technique for on-chip memory using biased partitioning and access concentration

Kawabe, N. & Usami, K., 2000, Proceedings of the Custom Integrated Circuits Conference. IEEE, p. 275-278 4 p.

研究成果: Conference contribution

Data storage equipment
Electric power utilization
2002
60 引用 (Scopus)

Automated selective multi-threshold design for ultra-low standby applications

Usami, K., Kawabe, N., Koizumi, M., Seta, K. & Furusawa, T., 2002, Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers. p. 202-206 5 p.

研究成果: Conference contribution

Transistors
Sleep
4 引用 (Scopus)

Code coverage-based power estimation techniques for microprocessors

Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2002 10, : : Journal of Circuits, Systems and Computers. 11, 5, p. 557-574 18 p.

研究成果: Article

Microprocessor chips
Embedded software
Energy dissipation
Energy utilization
Simulators
1 引用 (Scopus)
Code division multiple access
Transistors
Sleep
2004
11 引用 (Scopus)

A scheme to reduce active leakage power by detecting state transitions

Usami, K. & Yoshioka, H., 2004, Midwest Symposium on Circuits and Systems. 巻 1.

研究成果: Conference contribution

Testing
Degradation
Logic gates
Finite automata
Transistors
5 引用 (Scopus)
Finite automata
Transistors
Degradation
Combinatorial circuits
Logic gates
2005

Analysis on MTCMOS Circuits based on Lumped RC Model for Virtual Ground Line

K.Usami, K. U., N.Ohkubo, N. O., M.Shirakawa, M. S. & Usami, K., 2005 10 1, : : IEEE International SoC Design Conference 2005 (ISOCC'05). p. 116-119

研究成果: Article

2006
64 引用 (Scopus)

A design approach for fine-grained run-time power gating using locally extracted sleep signals

Usami, K. & Ohkubo, N., 2006, IEEE International Conference on Computer Design, ICCD 2006. p. 155-161 7 p. 4380809

研究成果: Conference contribution

Switches
Microprocessor chips
Clocks
Energy dissipation
Energy conservation
Delay circuits
Networks (circuits)
Electric potential
SPICE
Interpolation
5 引用 (Scopus)

Delay modeling and static timing analysis for MTCMOS circuits

Ohkubo, N. & Usami, K., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 巻 2006. p. 570-575 6 p. 1594746

研究成果: Conference contribution

Delay circuits
Networks (circuits)
Interpolation
Capacitance
Switches

Leakage in Nanometer CMOS Technologies -Methodologies for Power Gating

Usami, K., Sakurai, T. & authors., . M., 2006 10 1, : : Default journal. p. 77-104

研究成果: Article

2007
7 引用 (Scopus)

Overview on low power SoC design technology

Usami, K., 2007, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 634-636 3 p. 4196103

研究成果: Conference contribution

System-on-chip
2008
34 引用 (Scopus)

A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

Seki, N., Zhao, L., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Toshihiro Kashima, K., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M. & Nakamura, H., 2008, 26th IEEE International Conference on Computer Design 2008, ICCD. p. 612-617 6 p. 4751924

研究成果: Conference contribution

Tapes
Pipelines
Sleep
2 引用 (Scopus)

Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations

Shirai, T. & Usami, K., 2008, 2008 International SoC Design Conference, ISOCC 2008. 巻 1. 4815634

研究成果: Conference contribution

Networks (circuits)
Simulated annealing
Degradation
15 引用 (Scopus)

Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

Saito, Y., Shirai, T., Nakamura, T., Nishimura, T., Hasegawa, Y., Tsutsumi, S., Kashima, T., Nakata, M., Takeda, S., Usami, K. & Amano, H., 2008, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 329-332 4 p. 4762410

研究成果: Conference contribution

Parallel processing systems
Electric power utilization
Clocks
Processing

Power Gating for Ultra-low Leakage: Physics; Design; and Analysis

F.Jerry, F. J., K.Choi, K. C., K.Usami, K. U. & Usami, K., 2008 3 3, : : Design; Automation and Test in Europe 2008 (DATE'08).

研究成果: Article

2009
Controllers
Degradation
Networks (circuits)
25 引用 (Scopus)

Design and implementation of fine-grain power gating with ground bounce suppression

Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., Seki, N., Amano, H., Namiki, M., Imai, M., Kondo, M. & Nakamura, H., 2009, Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. p. 381-386 6 p. 4749703

研究成果: Conference contribution

Switches
Program processors
Energy dissipation
Temperature
Sleep
32 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyamat, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2009, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. p. 281-284 4 p. 5357257

研究成果: Conference contribution

Program processors
Electric power utilization
32 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with Fine Grain Runtime Power Gating

D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2009 11 16, : : IEEE Asian Solid-State Circuits Conference (A-SSCC) 2009. p. 281-284

研究成果: Article

7 引用 (Scopus)

Implementation and evaluation of fine-grain run-time power gating for a multiplier

Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H. & Nakamura, H., 2009, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. p. 7-10 4 p. 5166253

研究成果: Conference contribution

Energy conservation
Switches
Program processors
Analytical models
Energy dissipation
2010
7 引用 (Scopus)

Adaptive power gating for function units in a microprocessor

Usami, K., Hashida, T., Koyama, S., Yamamoto, T., Ikebuchi, D., Amano, H., Namiki, M., Kondo, M. & Nakamura, H., 2010, Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010. p. 29-37 9 p. 5450407

研究成果: Conference contribution

Microprocessor chips
Energy conservation
Temperature
Limiters
Analytical models
4 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2010, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 369-370 2 p. 5419857

研究成果: Conference contribution

Program processors
4 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2010 1 18, : : Default journal. p. 369-370

研究成果: Article

44 引用 (Scopus)

Ultra fine-grained run-time power gating of on-chip routers for CMPs

Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2010, NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. p. 61-68 8 p. 5507560

研究成果: Conference contribution

Routers
Circuit simulation
2011

A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS

Ozaki, N., Yasuda, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Symposium on Integrated Circuits, ISIC 2011. p. 579-584 6 p. 6131929

研究成果: Conference contribution

Combinatorial circuits
Particle accelerators
Processing
Data flow graphs
Data storage equipment