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研究成果 1987 2019

  • 1605 引用
  • 20 h指数
  • 68 Conference contribution
  • 36 Article
  • 1 Chapter
13 引用 (Scopus)

60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Tsuboi, Y., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Momose, H. & Usami, K., 1998, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Anon (版). IEEE, p. 36-37 2 p.

研究成果: Conference contribution

Energy dissipation
Electric potential
Motion pictures
Networks (circuits)
Threshold voltage

A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS

Ozaki, N., Yasuda, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Symposium on Integrated Circuits, ISIC 2011. p. 579-584 6 p. 6131929

研究成果: Conference contribution

Combinatorial circuits
Particle accelerators
Processing
Data flow graphs
Data storage equipment
72 引用 (Scopus)

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Usami, K., Igarashi, M., Ishikawa, T., Kanazawa, M., Kuroda, T. & Furuyama, T., 1998 11, : : IEEE Journal of Solid-State Circuits. 33, 11, p. 1772-1778 7 p.

研究成果: Article

Energy dissipation
Static random access storage
Electric potential
Computer hardware
Decoding

A coarse grained-reconfigurable accelerator with energy efficient MTJ-based non-volatile flip-flops

Ikezoe, T., Amano, H., Akaike, J., Usami, K., Kudo, M., Hiraga, K., Shuto, Y. & Yagami, K., 2019 2 13, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018. Andrews, D., Feregrino, C., Cumplido, R. & Stroobandt, D. (版). Institute of Electrical and Electronics Engineers Inc., 8641712. (2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018).

研究成果: Conference contribution

Flip flop circuits
Particle accelerators
Data storage equipment
Managers
Inventory control
7 引用 (Scopus)

Adaptive power gating for function units in a microprocessor

Usami, K., Hashida, T., Koyama, S., Yamamoto, T., Ikebuchi, D., Amano, H., Namiki, M., Kondo, M. & Nakamura, H., 2010, Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010. p. 29-37 9 p. 5450407

研究成果: Conference contribution

Microprocessor chips
Energy conservation
Temperature
Limiters
Analytical models
64 引用 (Scopus)

A design approach for fine-grained run-time power gating using locally extracted sleep signals

Usami, K. & Ohkubo, N., 2006, IEEE International Conference on Computer Design, ICCD 2006. p. 155-161 7 p. 4380809

研究成果: Conference contribution

Switches
Microprocessor chips
Clocks
Energy dissipation
Energy conservation
34 引用 (Scopus)

A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

Seki, N., Zhao, L., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Toshihiro Kashima, K., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M. & Nakamura, H., 2008, 26th IEEE International Conference on Computer Design 2008, ICCD. p. 612-617 6 p. 4751924

研究成果: Conference contribution

Tapes
Pipelines
Sleep
2 引用 (Scopus)

A fine-grained power gating control on linux monitoring power consumption of processor functional units

Koshiba, A., Wada, M., Sakamoto, R., Sato, M., Kosaka, T., Usami, K., Amano, H., Kondo, M., Nakamura, H. & Namiki, M., 2015 7 1, : : IEICE Transactions on Electronics. E98C, 7, p. 559-568 10 p.

研究成果: Article

Electric power utilization
Monitoring
Electric potential
Microprocessor chips
Switches

A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control

Okuhara, H., Usami, K. & Amano, H., 2015 7 14, IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVIII - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7158656

研究成果: Conference contribution

Bias voltage
Leakage currents
Detectors
Silicon
Networks (circuits)
14 引用 (Scopus)

A multi-Vdd dynamic variable-pipeline on-chip router for CMPs

Matsutani, H., Hirata, Y., Koibuchi, M., Usami, K., Nakamura, H. & Amano, H., 2012, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 407-412 6 p. 6164982

研究成果: Conference contribution

Routers
Pipelines
Electric potential
Electric power utilization
Simulators

Analysis on MTCMOS Circuits based on Lumped RC Model for Virtual Ground Line

K.Usami, K. U., N.Ohkubo, N. O., M.Shirakawa, M. S. & Usami, K., 2005 10 1, : : IEEE International SoC Design Conference 2005 (ISOCC'05). p. 116-119

研究成果: Article

1 引用 (Scopus)
Clocks
Energy conservation
Synchronization
Energy utilization
Communication

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533808

研究成果: Conference contribution

Electric potential
Energy conservation
Scheduling
High level synthesis

An operating system guided fine-grained power gating control based on runtime characteristics of applications

Koshiba, A., Sato, M., Usami, K., Amano, H., Sakamoto, R., Kondo, M., Nakamura, H. & Namiki, M., 2016 8 1, : : IEICE Transactions on Electronics. E99C, 8, p. 926-935 10 p.

研究成果: Article

Electric power utilization
Application programs
Computer monitors
Networks (circuits)
12 引用 (Scopus)

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

Okuhara, H., Kitamori, K., Fujita, Y., Usami, K. & Amano, H., 2015 9 21, Proceedings of the International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 巻 2015-September. p. 207-212 6 p. 7273515

研究成果: Conference contribution

Bias voltage
Silicon
Controllers
Oxides
Electric potential

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Kamohara, S., Sugii, N., Ishibashi, K., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2016 5 25, 2014 IEEE Hot Chips 26 Symposium, HCS 2014. Institute of Electrical and Electronics Engineers Inc., 7478838

研究成果: Conference contribution

Program processors
Sleep
17 引用 (Scopus)

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Ishibashi, K., Sugii, N., Kamohara, S., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2015 7 1, : : IEICE Transactions on Electronics. E98C, 7, p. 536-543 8 p.

研究成果: Article

Program processors
Wearable computers
Harvesters
Energy harvesting
Silicon
20 引用 (Scopus)

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Ishibashi, K., Sugii, N., Usami, K., Amano, H., Kobayashi, K., Pham, C. K., Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Yamaguchi, Y., Oda, H., Hasegawa, T., Okanishi, S., Yanagita, H., Kamohara, S., Kadoshima, M., Maekawa, K., Yamashita, T., Le, D. H. および5人, Yomogita, T., Kudo, M., Kitamori, K., Kondo, S. & Manzawa, Y., 2014, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society, 6842954

研究成果: Conference contribution

Program processors
Silicon
Oxides
Sleep

Approximate Computing Technique Using Memoization and Simplified Multiplication

Ono, Y. & Usami, K., 2019 6 1, 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 8793369. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

研究成果: Conference contribution

Energy utilization
Embedded systems
Ion exchange

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2016 5 24, 2013 IEEE Hot Chips 25 Symposium, HCS 2013. Institute of Electrical and Electronics Engineers Inc., 7478328

研究成果: Conference contribution

Particle accelerators
Reconfigurable architectures
Program processors
Scalability
Masks
1 引用 (Scopus)

A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 6547916

研究成果: Conference contribution

Particle accelerators
Energy efficiency
Parallel processing systems
Program processors
Costs
20 引用 (Scopus)

A scalable 3D heterogeneous multicore with an inductive ThruChip interface

Miura, N., Koizumi, Y., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 11, : : IEEE Micro. 33, 6, p. 6-15 10 p., 6684194.

研究成果: Article

Particle accelerators
Program processors
Costs
Energy utilization
Communication
11 引用 (Scopus)

A scheme to reduce active leakage power by detecting state transitions

Usami, K. & Yoshioka, H., 2004, Midwest Symposium on Circuits and Systems. 巻 1.

研究成果: Conference contribution

Testing
Degradation
Logic gates
Finite automata
Transistors
2 引用 (Scopus)

A thermal management system for building block computing systems

Fujita, Y., Usami, K. & Amano, H., 2014 11 6, Proceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014. Institute of Electrical and Electronics Engineers Inc., p. 165-171 7 p. 6949468

研究成果: Conference contribution

Temperature control
Heat losses
Temperature
Temperature sensors
Voltage control
22 引用 (Scopus)

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Usami, K., Nogami, K., Igarashi, M., Minami, F., Kawasaki, Y., Ishikawa, T., Kanazawa, M., Aoki, T., Takano, M., Mizuno, C., Ichida, M., Sonoda, S., Takahashi, M. & Hatanaka, N., 1997, Proceedings of the Custom Integrated Circuits Conference. IEEE, p. 131-134 4 p.

研究成果: Conference contribution

Electric potential
191 引用 (Scopus)

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Usami, K., Igarashi, M., Minami, F., Ishikawa, T., Kanazawa, M., Ichida, M. & Nogami, K., 1998 3, : : IEEE Journal of Solid-State Circuits. 33, 3, p. 463-471 9 p.

研究成果: Article

Electric potential
Clocks
60 引用 (Scopus)

Automated selective multi-threshold design for ultra-low standby applications

Usami, K., Kawabe, N., Koizumi, M., Seta, K. & Furusawa, T., 2002, Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers. p. 202-206 5 p.

研究成果: Conference contribution

Transistors
Sleep

Building block multi-chip systems using inductive coupling through chip interface

Amano, H., Kuroda, T., Nakamura, H., Usami, K., Kondo, M., Matsutani, H. & Namiki, M., 2018 5 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 152-154 3 p.

研究成果: Conference contribution

Computer operating systems
Network architecture
Interfaces (computer)
Networks (circuits)
Hot Temperature
Controllers
Degradation
Networks (circuits)
12 引用 (Scopus)

Clock-gating method for low-power LSI design

Kitahara, T., Minami, F., Ueda, T., Usami, K., Nishio, S., Murakata, M. & Mitsuhashi, T., 1998, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE, p. 307-312 6 p.

研究成果: Chapter

Clocks
Networks (circuits)
322 引用 (Scopus)

Clustered voltage scaling technique for low-power design

Usami, K. & Horowitz, M., 1995, Proceedings of the International Symposium on Low Power Design. New York, NY, United States: ACM, p. 3-8 6 p.

研究成果: Conference contribution

Networks (circuits)
Electric potential
Microprocessor chips
Voltage scaling
3 引用 (Scopus)

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect

Koizumi, Y., Sasaki, E., Amano, H., Matsutani, H., Take, Y., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 543-546 4 p. 6339375

研究成果: Conference contribution

Particle accelerators
Combinatorial circuits
Packet switching
Packet networks
Switching networks
4 引用 (Scopus)

Code coverage-based power estimation techniques for microprocessors

Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2002 10, : : Journal of Circuits, Systems and Computers. 11, 5, p. 557-574 18 p.

研究成果: Article

Microprocessor chips
Embedded software
Energy dissipation
Energy utilization
Simulators
13 引用 (Scopus)

Cool mega-array: A highly energy efficient reconfigurable accelerator

Ozaki, N., Yoshihiro, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132668

研究成果: Conference contribution

Particle accelerators
Processing
Controllers
Information management
Electric power utilization
37 引用 (Scopus)

Cool mega-arrays: Ultralow-power reconfigurable accelerator chips

Ozaki, N., Yasuda, Y., Izawa, M., Saito, Y., Ikebuchi, D., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011 11, : : IEEE Micro. 31, 6, p. 6-18 13 p., 6060791.

研究成果: Article

Particle accelerators
Data flow graphs
Data storage equipment
Microcontrollers
Mobile devices
1 引用 (Scopus)

Datapath generator based on gate-level symbolic layout

Matsumoto, N., Watanabe, Y., Usami, K., Sugeno, Y., Hatada, H. & Mori, S., 1990, 27th ACM/IEEE Design Automation Conference. Proceedings 1990. Piscataway, NJ, United States: Publ by IEEE, p. 388-393 6 p.

研究成果: Conference contribution

Masks
Transistors
Delay circuits
Networks (circuits)
Electric potential
SPICE
Interpolation
5 引用 (Scopus)

Delay modeling and static timing analysis for MTCMOS circuits

Ohkubo, N. & Usami, K., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 巻 2006. p. 570-575 6 p. 1594746

研究成果: Conference contribution

Delay circuits
Networks (circuits)
Interpolation
Capacitance
Switches

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links

Koizumi, Y., Miura, N., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013, 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings. IEEE Computer Society, 6645628

研究成果: Conference contribution

Particle accelerators
Demonstrations
Electric potential
Program processors
Energy utilization
9 引用 (Scopus)

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors

Usami, K., Kudo, M., Matsunaga, K., Kosaka, T., Tsurui, Y., Wang, W., Amano, H., Kobayashi, H., Sakamoto, R., Namiki, M., Kondo, M. & Nakamura, H., 2014, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 843-848 6 p. 6742995

研究成果: Conference contribution

Microprocessor chips
Energy dissipation
Temperature
Sleep
14 引用 (Scopus)

Design and evaluation of fine-grained power-gating for embedded microprocessors

Kondo, M., Kobyashi, H., Sakamoto, R., Wada, M., Tsukamoto, J., Namiki, M., Wang, W., Amano, H., Matsunaga, K., Kudo, M., Usami, K., Komoda, T. & Nakamura, H., 2014, Proceedings -Design, Automation and Test in Europe, DATE. Institute of Electrical and Electronics Engineers Inc., 6800359

研究成果: Conference contribution

Microprocessor chips
Electric power utilization
Hardware
Leakage currents
Temperature
3 引用 (Scopus)

Design and implementation fine-grained power gating on microprocessor functional units

Lei, Z., Ikebuchi, D., Usami, K., Namiki, M., Kondo, M., Nakamura, H. & Amano, H., 2011, : : IPSJ Transactions on System LSI Design Methodology. 4, p. 182-192 11 p.

研究成果: Article

Microprocessor chips
Electric power utilization
1 引用 (Scopus)

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

Yoshida, Y. & Usami, K., 2017 6 29, Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 43-46 4 p. 7962596

研究成果: Conference contribution

Silicon
methodology
Data storage equipment
silicon
cells
25 引用 (Scopus)

Design and implementation of fine-grain power gating with ground bounce suppression

Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., Seki, N., Amano, H., Namiki, M., Imai, M., Kondo, M. & Nakamura, H., 2009, Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. p. 381-386 6 p. 4749703

研究成果: Conference contribution

Switches
Program processors
Energy dissipation
Temperature
Sleep

DESIGN METHODOLOGY OF STANDARD CELL LAYOUT AND PLA.

Usami, K., Ishii, A., Horie, A. & Iwamura, J., 1987, Proceedings of the Custom Integrated Circuits Conference. IEEE, p. 379-384 6 p.

研究成果: Conference contribution

Fans
Macros
29 引用 (Scopus)

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

Usami, K., Igarashi, M., Ishikawa, T., Kanazawa, M., Takahashi, M., Hamada, M., Arakida, H., Terazawa, T. & Kuroda, T., 1998, Proceedings - Design Automation Conference. IEEE, p. 483-488 6 p.

研究成果: Conference contribution

Turnaround time
Electric potential
Voltage scaling
4 引用 (Scopus)

Design of a 32bit microprocessor, TX1

Tokumaru, T., Masuda, E., Hori, C., Usami, K., Miyata, M. & Iwamura, J., 1988, 1988 Symp VLSI Circuits Dig Tech Pap. Anon (版). p. 33-34 2 p.

研究成果: Conference contribution

Microprocessor chips
Routers
Clocks
Automation
Logic Synthesis
1 引用 (Scopus)

Design of a 32-bit microprocessor, TX1

Tokumaru, T., Masuda, E., Usami, K., Usami, K., Miyata, M. & Iwamura, J., 1989 8, : : IEEE Journal of Solid-State Circuits. 24, 4, p. 938-944 7 p.

研究成果: Article

Microprocessor chips
Design for testability
Clocks
Transistors
Metals