• 1634 引用
  • 20 h指数
1987 …2020

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

Article

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Usami, K., Igarashi, M., Ishikawa, T., Kanazawa, M., Kuroda, T. & Furuyama, T., 1998 11 1, : : IEEE Journal of Solid-State Circuits. 33, 11, p. 1772-1778 7 p.

研究成果: Article

72 引用 (Scopus)

A fine-grained power gating control on linux monitoring power consumption of processor functional units

Koshiba, A., Wada, M., Sakamoto, R., Sato, M., Kosaka, T., Usami, K., Amano, H., Kondo, M., Nakamura, H. & Namiki, M., 2015 7 1, : : IEICE Transactions on Electronics. E98C, 7, p. 559-568 10 p.

研究成果: Article

2 引用 (Scopus)

Analysis on MTCMOS Circuits based on Lumped RC Model for Virtual Ground Line

K.Usami, K. U., N.Ohkubo, N. O., M.Shirakawa, M. S. & Usami, K., 2005 10 1, : : IEEE International SoC Design Conference 2005 (ISOCC'05). p. 116-119

研究成果: Article

1 引用 (Scopus)

An operating system guided fine-grained power gating control based on runtime characteristics of applications

Koshiba, A., Sato, M., Usami, K., Amano, H., Sakamoto, R., Kondo, M., Nakamura, H. & Namiki, M., 2016 8 1, : : IEICE Transactions on Electronics. E99C, 8, p. 926-935 10 p.

研究成果: Article

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Ishibashi, K., Sugii, N., Kamohara, S., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2015 7 1, : : IEICE Transactions on Electronics. E98C, 7, p. 536-543 8 p.

研究成果: Article

17 引用 (Scopus)

A scalable 3D heterogeneous multicore with an inductive ThruChip interface

Miura, N., Koizumi, Y., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 11 1, : : IEEE Micro. 33, 6, p. 6-15 10 p., 6684194.

研究成果: Article

21 引用 (Scopus)

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Usami, K., Igarashi, M., Minami, F., Ishikawa, T., Kanazawa, M., Ichida, M. & Nogami, K., 1998 3 1, : : IEEE Journal of Solid-State Circuits. 33, 3, p. 463-472 10 p.

研究成果: Article

198 引用 (Scopus)

Code coverage-based power estimation techniques for microprocessors

Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2002 10 1, : : Journal of Circuits, Systems and Computers. 11, 5, p. 557-574 18 p.

研究成果: Article

4 引用 (Scopus)

Cool mega-arrays: Ultralow-power reconfigurable accelerator chips

Ozaki, N., Yasuda, Y., Izawa, M., Saito, Y., Ikebuchi, D., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011 11 1, : : IEEE Micro. 31, 6, p. 6-18 13 p., 6060791.

研究成果: Article

39 引用 (Scopus)

Design and implementation fine-grained power gating on microprocessor functional units

Lei, Z., Ikebuchi, D., Usami, K., Namiki, M., Kondo, M., Nakamura, H. & Amano, H., 2011, : : IPSJ Transactions on System LSI Design Methodology. 4, p. 182-192 11 p.

研究成果: Article

3 引用 (Scopus)

Design of a 32-bit Microprocessor, TX1

Tokumaru, T., Masuda, E., Usami, K., Miyata, M., Iwamura, J. & Hori, C., 1989 8, : : IEEE Journal of Solid-State Circuits. 24, 4, p. 938-944 7 p.

研究成果: Article

1 引用 (Scopus)
5 引用 (Scopus)

Fine-grained run-tume power gating through co-optimization of circuit, architecture, and system software design

Nakamura, H., Wang, W., Ohta, Y., Usami, K., Amano, H., Kondo, M. & Namiki, M., 2013 4, : : IEICE Transactions on Electronics. E96-C, 4, p. 404-412 9 p.

研究成果: Article

2 引用 (Scopus)

Function-level power estimation methodology for microprocessors

Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2000 1 1, : : Proceedings-Design Automation Conference. p. 810-813 4 p.

研究成果: Article

66 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2010 1 18, : : Default journal. p. 369-370

研究成果: Article

4 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with Fine Grain Runtime Power Gating

D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2009 11 16, : : IEEE Asian Solid-State Circuits Conference (A-SSCC) 2009. p. 281-284

研究成果: Article

33 引用 (Scopus)

Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011 1 26, : : 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011. p. 87-88

研究成果: Article

10 引用 (Scopus)

Hierarchical Symbolic Design Methodology for Large-Scale Data Paths

Usami, K., Sugeno, Y., Matsumoto, N. & Mori, S., 1991 3, : : IEEE Journal of Solid-State Circuits. 26, 3, p. 381-385 5 p.

研究成果: Article

Leakage in Nanometer CMOS Technologies -Methodologies for Power Gating

Usami, K., Sakurai, T. & authors., . M., 2006 10 1, : : Default journal. p. 77-104

研究成果: Article

Multi-voltage variable pipeline routers with the same clock frequency for low-power network-on-chips systems

Ahmed, A. B., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2016 8 1, : : IEICE Transactions on Electronics. E99C, 8, p. 909-917 9 p.

研究成果: Article

2 引用 (Scopus)

Performance, area, and power evaluations of ultrafine-grained run-time power-gating routers for CMPs

Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2011 4 1, : : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 4, p. 520-533 14 p., 5737865.

研究成果: Article

29 引用 (Scopus)

Power Gating for Ultra-low Leakage: Physics; Design; and Analysis

F.Jerry, F. J., K.Choi, K. C., K.Usami, K. U. & Usami, K., 2008 3 3, : : Design; Automation and Test in Europe 2008 (DATE'08).

研究成果: Article

10 引用 (Scopus)
1 引用 (Scopus)
1 引用 (Scopus)
Conference article

60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Tsuboi, Y., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Momose, H. & Usami, K., 1998 1 1, : : Digest of Technical Papers - IEEE International Solid-State Circuits Conference. p. 36-37 2 p.

研究成果: Conference article

13 引用 (Scopus)

A scheme to reduce active leakage power by detecting state transitions

Usami, K. & Yoshioka, H., 2004 12 1, : : Midwest Symposium on Circuits and Systems. 1, p. I493-I496

研究成果: Conference article

11 引用 (Scopus)

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Usami, K., Nogami, K., Igarashi, M., Minami, F., Kawasaki, Y., Ishikawa, T., Kanazawa, M., Aoki, T., Takano, M., Mizuno, C., Ichida, M., Sonoda, S., Takahashi, M. & Hatanaka, N., 1997 1 1, : : Proceedings of the Custom Integrated Circuits Conference. p. 131-134 4 p.

研究成果: Conference article

22 引用 (Scopus)

Cache controller design on ultra low leakage embedded processors

Lei, Z., Xu, H., Seki, N., Yoshiki, S., Hasegawa, Y., Usami, K. & Amano, H., 2009 4 6, : : Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5455 LNCS, p. 171-182 12 p.

研究成果: Conference article

DESIGN METHODOLOGY OF STANDARD CELL LAYOUT AND PLA.

Usami, K., Ishii, A., Horie, A. & Iwamura, J., 1987 1 1, : : Proceedings of the Custom Integrated Circuits Conference. p. 379-384 6 p.

研究成果: Conference article

Hierarchical symbolic design methodology for large-scale datapaths

Usami, K., Sugeno, Y., Matsumoto, N. & Mori, S., 1990 12 1, : : Proceedings of the Custom Integrated Circuits Conference.

研究成果: Conference article

1 引用 (Scopus)

Low-power design technique for ASICs by partially reducing supply voltage

Usami, K., Ishikawa, T., Kanazawa, M. & Kotani, H., 1996 1 1, : : Proceedings of the Annual IEEE International ASIC Conference and Exhibit. p. 301-304 4 p.

研究成果: Conference article

24 引用 (Scopus)
6 引用 (Scopus)

Optimized design method for full-custom microprocessors

Usami, K. & Iwamura, J., 1989 12 1, : : Proceedings of the Custom Integrated Circuits Conference. p. 19.5.1-19.5.5 5726257.

研究成果: Conference article

1 引用 (Scopus)

Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

Hamada, M., Takahashi, M., Arakida, H., Chiba, A., Terazawa, T., Ishikawa, T., Kanazawa, M., Igarashi, M., Usami, K. & Kuroda, T., 1998 1 1, : : Proceedings of the Custom Integrated Circuits Conference. p. 495-498 4 p.

研究成果: Conference article

80 引用 (Scopus)
Conference contribution

A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS

Ozaki, N., Yasuda, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Symposium on Integrated Circuits, ISIC 2011. p. 579-584 6 p. 6131929. (2011 International Symposium on Integrated Circuits, ISIC 2011).

研究成果: Conference contribution

A coarse grained-reconfigurable accelerator with energy efficient MTJ-based non-volatile flip-flops

Ikezoe, T., Amano, H., Akaike, J., Usami, K., Kudo, M., Hiraga, K., Shuto, Y. & Yagami, K., 2019 2 13, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018. Andrews, D., Feregrino, C., Cumplido, R. & Stroobandt, D. (版). Institute of Electrical and Electronics Engineers Inc., 8641712. (2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018).

研究成果: Conference contribution

2 引用 (Scopus)

Adaptive power gating for function units in a microprocessor

Usami, K., Hashida, T., Koyama, S., Yamamoto, T., Ikebuchi, D., Amano, H., Namiki, M., Kondo, M. & Nakamura, H., 2010, Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010. p. 29-37 9 p. 5450407. (Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010).

研究成果: Conference contribution

7 引用 (Scopus)

A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

Seki, N., Zhao, L., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Toshihiro Kashima, K., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M. & Nakamura, H., 2008 12 1, 26th IEEE International Conference on Computer Design 2008, ICCD. p. 612-617 6 p. 4751924. (26th IEEE International Conference on Computer Design 2008, ICCD).

研究成果: Conference contribution

34 引用 (Scopus)

A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control

Okuhara, H., Usami, K. & Amano, H., 2015 7 14, IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVIII - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7158656

研究成果: Conference contribution

A multi-Vdd dynamic variable-pipeline on-chip router for CMPs

Matsutani, H., Hirata, Y., Koibuchi, M., Usami, K., Nakamura, H. & Amano, H., 2012 4 26, ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. p. 407-412 6 p. 6164982. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

14 引用 (Scopus)