• 1628 引用
  • 20 h指数
1987 …2020

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

2011

Dynamic VDD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

Yamamoto, T., Hironaka, K., Hayakawa, Y., Kimura, M., Amano, H. & Usami, K., 2011 4 4, Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Proceedings. p. 230-241 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 巻数 6578 LNCS).

研究成果: Conference contribution

9 引用 (Scopus)

Geyser-2: The second prototype CPU with fine-grained run-time power gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011 3 28, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. p. 87-88 2 p. 5722310. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

10 引用 (Scopus)

Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011 1 26, : : 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011. p. 87-88

研究成果: Article

10 引用 (Scopus)

On-chip detection methodology for break-even time of power gated function units

Usami, K., Goto, Y., Matsunaga, K., Koyama, S., Ikebuchi, D., Amano, H. & Nakamura, H., 2011 9 19, IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. p. 241-246 6 p. 5993643. (Proceedings of the International Symposium on Low Power Electronics and Design).

研究成果: Conference contribution

13 引用 (Scopus)

Performance, area, and power evaluations of ultrafine-grained run-time power-gating routers for CMPs

Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2011 4 1, : : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 4, p. 520-533 14 p., 5737865.

研究成果: Article

29 引用 (Scopus)

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H. & Kondo, M., 2011 7 18, IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 5890918. (IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings).

研究成果: Conference contribution

2 引用 (Scopus)
1 引用 (Scopus)
2010

Adaptive power gating for function units in a microprocessor

Usami, K., Hashida, T., Koyama, S., Yamamoto, T., Ikebuchi, D., Amano, H., Namiki, M., Kondo, M. & Nakamura, H., 2010 5 28, Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010. p. 29-37 9 p. 5450407. (Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010).

研究成果: Conference contribution

7 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2010 1 18, : : Default journal. p. 369-370

研究成果: Article

4 引用 (Scopus)

Ultra fine-grained run-time power gating of on-chip routers for CMPs

Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2010 8 5, NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. p. 61-68 8 p. 5507560. (NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip).

研究成果: Conference contribution

46 引用 (Scopus)
2009

Cache controller design on ultra low leakage embedded processors

Lei, Z., Xu, H., Seki, N., Yoshiki, S., Hasegawa, Y., Usami, K. & Amano, H., 2009 4 6, : : Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5455 LNCS, p. 171-182 12 p.

研究成果: Conference article

Design and implementation of fine-grain power gating with ground bounce suppression

Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., Seki, N., Amano, H., Namiki, M., Imai, M., Kondo, M. & Nakamura, H., 2009 3 30, Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. p. 381-386 6 p. 4749703. (Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems).

研究成果: Conference contribution

25 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyamat, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2009 12 1, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. p. 281-284 4 p. 5357257. (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009).

研究成果: Conference contribution

33 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with Fine Grain Runtime Power Gating

D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2009 11 16, : : IEEE Asian Solid-State Circuits Conference (A-SSCC) 2009. p. 281-284

研究成果: Article

33 引用 (Scopus)

Implementation and evaluation of fine-grain run-time power gating for a multiplier

Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H. & Nakamura, H., 2009 12 1, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. p. 7-10 4 p. 5166253. (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009).

研究成果: Conference contribution

7 引用 (Scopus)
2008

A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

Seki, N., Zhao, L., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Toshihiro Kashima, K., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M. & Nakamura, H., 2008 12 1, 26th IEEE International Conference on Computer Design 2008, ICCD. p. 612-617 6 p. 4751924. (26th IEEE International Conference on Computer Design 2008, ICCD).

研究成果: Conference contribution

34 引用 (Scopus)

Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations

Shirai, T. & Usami, K., 2008 12 1, 2008 International SoC Design Conference, ISOCC 2008. p. I310-I313 4815634. (2008 International SoC Design Conference, ISOCC 2008; 巻数 1).

研究成果: Conference contribution

2 引用 (Scopus)

Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

Saito, Y., Shirai, T., Nakamura, T., Nishimura, T., Hasegawa, Y., Tsutsumi, S., Kashima, T., Nakata, M., Takeda, S., Usami, K. & Amano, H., 2008 12 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 329-332 4 p. 4762410. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

研究成果: Conference contribution

15 引用 (Scopus)

Power Gating for Ultra-low Leakage: Physics; Design; and Analysis

F.Jerry, F. J., K.Choi, K. C., K.Usami, K. U. & Usami, K., 2008 3 3, : : Design; Automation and Test in Europe 2008 (DATE'08).

研究成果: Article

2007

Overview on low power SoC design technology

Usami, K., 2007 12 1, Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. p. 634-636 3 p. 4196103. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

7 引用 (Scopus)
2006
65 引用 (Scopus)

Delay modeling and static timing analysis for MTCMOS circuits

Ohkubo, N. & Usami, K., 2006 9 19, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. p. 570-575 6 p. 1594746. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 巻数 2006).

研究成果: Conference contribution

5 引用 (Scopus)

Leakage in Nanometer CMOS Technologies -Methodologies for Power Gating

Usami, K., Sakurai, T. & authors., . M., 2006 10 1, : : Default journal. p. 77-104

研究成果: Article

2005

Analysis on MTCMOS Circuits based on Lumped RC Model for Virtual Ground Line

K.Usami, K. U., N.Ohkubo, N. O., M.Shirakawa, M. S. & Usami, K., 2005 10 1, : : IEEE International SoC Design Conference 2005 (ISOCC'05). p. 116-119

研究成果: Article

2004

A scheme to reduce active leakage power by detecting state transitions

Usami, K. & Yoshioka, H., 2004 12 1, : : Midwest Symposium on Circuits and Systems. 1, p. I493-I496

研究成果: Conference article

11 引用 (Scopus)
5 引用 (Scopus)
2002

Automated selective multi-threshold design for ultra-low standby applications

Usami, K., Kawabe, N., Koizumi, M., Seta, K. & Furusawa, T., 2002, p. 202-206. 5 p.

研究成果: Paper

60 引用 (Scopus)

Code coverage-based power estimation techniques for microprocessors

Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2002 10 1, : : Journal of Circuits, Systems and Computers. 11, 5, p. 557-574 18 p.

研究成果: Article

4 引用 (Scopus)
1 引用 (Scopus)
2000

Function-level power estimation methodology for microprocessors

Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2000 1 1, : : Proceedings-Design Automation Conference. p. 810-813 4 p.

研究成果: Article

66 引用 (Scopus)

Low-power design methodology and applications utilizing dual supply voltages

Usami, K. & Igarashi, M., 2000 12 1, Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000. p. 123-128 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

30 引用 (Scopus)
6 引用 (Scopus)
1998

60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Tsuboi, Y., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Momose, H. & Usami, K., 1998 1 1, : : Digest of Technical Papers - IEEE International Solid-State Circuits Conference. p. 36-37 2 p.

研究成果: Conference article

13 引用 (Scopus)

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Usami, K., Igarashi, M., Ishikawa, T., Kanazawa, M., Kuroda, T. & Furuyama, T., 1998 11 1, : : IEEE Journal of Solid-State Circuits. 33, 11, p. 1772-1778 7 p.

研究成果: Article

72 引用 (Scopus)

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Usami, K., Igarashi, M., Minami, F., Ishikawa, T., Kanazawa, M., Ichida, M. & Nogami, K., 1998 3 1, : : IEEE Journal of Solid-State Circuits. 33, 3, p. 463-472 10 p.

研究成果: Article

196 引用 (Scopus)

Clock-gating method for low-power LSI design

Kitahara, T., Minami, F., Ueda, T., Usami, K., Nishio, S., Murakata, M. & Mitsuhashi, T., 1998 12 1, p. 307-312. 6 p.

研究成果: Paper

12 引用 (Scopus)

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

Usami, K., Lgarashi, M., Ishikawa, T., Kanazawa, M., Takahashi, M., Hamada, M. & Arakida, H., 1998 1 1, Proceedings 1998 - Design and Automation Conference, DAC 1998. Institute of Electrical and Electronics Engineers Inc., p. 483-488 6 p. 724520. (Proceedings - Design Automation Conference).

研究成果: Conference contribution

29 引用 (Scopus)

Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

Hamada, M., Takahashi, M., Arakida, H., Chiba, A., Terazawa, T., Ishikawa, T., Kanazawa, M., Igarashi, M., Usami, K. & Kuroda, T., 1998 1 1, : : Proceedings of the Custom Integrated Circuits Conference. p. 495-498 4 p.

研究成果: Conference article

79 引用 (Scopus)
1997

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Usami, K., Nogami, K., Igarashi, M., Minami, F., Kawasaki, Y., Ishikawa, T., Kanazawa, M., Aoki, T., Takano, M., Mizuno, C., Ichida, M., Sonoda, S., Takahashi, M. & Hatanaka, N., 1997 1 1, : : Proceedings of the Custom Integrated Circuits Conference. p. 131-134 4 p.

研究成果: Conference article

22 引用 (Scopus)

Low-power design method using multiple supply voltages

Igarashi, M., Usami, K., Nogami, K., Minami, F., Kawasaki, Y., Aoki, T., Takano, M., Mizuno, C., Lshikawa, T., Kanazawa, M., Sonoda, S., Ichida, M. & Hatanaka, N., 1997 1 1, p. 36-41. 6 p.

研究成果: Paper

52 引用 (Scopus)
1996

Low-power design technique for ASICs by partially reducing supply voltage

Usami, K., Ishikawa, T., Kanazawa, M. & Kotani, H., 1996 1 1, : : Proceedings of the Annual IEEE International ASIC Conference and Exhibit. p. 301-304 4 p.

研究成果: Conference article

24 引用 (Scopus)
1995

Clustered voltage scaling technique for low-power design

Usami, K. & Horowitz, M., 1995, p. 3-8. 6 p.

研究成果: Paper

322 引用 (Scopus)
1991

Hierarchical Symbolic Design Methodology for Large-Scale Data Paths

Usami, K., Sugeno, Y., Matsumoto, N. & Mori, S., 1991 3, : : IEEE Journal of Solid-State Circuits. 26, 3, p. 381-385 5 p.

研究成果: Article

1990

Datapath generator based on gate-level symbolic layout

Matsumoto, N., Watanabe, Y., Usami, K., Sugeno, Y., Hatada, H. & Mori, S., 1990 1 1, 27th ACM/IEEE Design Automation Conference. Proceedings 1990. Publ by IEEE, p. 388-393 6 p. (27th ACM/IEEE Design Automation Conference. Proceedings 1990).

研究成果: Conference contribution

1 引用 (Scopus)