• 1628 引用
  • 20 h指数
1987 …2020

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

Conference contribution

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013 8 15, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533808. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

研究成果: Conference contribution

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

Okuhara, H., Kitamori, K., Fujita, Y., Usami, K. & Amano, H., 2015 9 21, Proceedings of the International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 巻 2015-September. p. 207-212 6 p. 7273515

研究成果: Conference contribution

13 引用 (Scopus)

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Kamohara, S., Sugii, N., Ishibashi, K., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2016 5 25, 2014 IEEE Hot Chips 26 Symposium, HCS 2014. Institute of Electrical and Electronics Engineers Inc., 7478838

研究成果: Conference contribution

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Ishibashi, K., Sugii, N., Usami, K., Amano, H., Kobayashi, K., Pham, C. K., Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Yamaguchi, Y., Oda, H., Hasegawa, T., Okanishi, S., Yanagita, H., Kamohara, S., Kadoshima, M., Maekawa, K., Yamashita, T., Le, D. H. および5人, Yomogita, T., Kudo, M., Kitamori, K., Kondo, S. & Manzawa, Y., 2014 1 1, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society, 6842954. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII).

研究成果: Conference contribution

20 引用 (Scopus)

Approximate Computing Technique Using Memoization and Simplified Multiplication

Ono, Y. & Usami, K., 2019 6, 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 8793369. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

研究成果: Conference contribution

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2016 5 24, 2013 IEEE Hot Chips 25 Symposium, HCS 2013. Institute of Electrical and Electronics Engineers Inc., 7478328. (2013 IEEE Hot Chips 25 Symposium, HCS 2013).

研究成果: Conference contribution

A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 8 15, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 6547916. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI).

研究成果: Conference contribution

1 引用 (Scopus)

A thermal management system for building block computing systems

Fujita, Y., Usami, K. & Amano, H., 2014 11 6, Proceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014. Institute of Electrical and Electronics Engineers Inc., p. 165-171 7 p. 6949468. (Proceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014).

研究成果: Conference contribution

2 引用 (Scopus)

Building block multi-chip systems using inductive coupling through chip interface

Amano, H., Kuroda, T., Nakamura, H., Usami, K., Kondo, M., Matsutani, H. & Namiki, M., 2018 5 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 152-154 3 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

研究成果: Conference contribution

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect

Koizumi, Y., Sasaki, E., Amano, H., Matsutani, H., Take, Y., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012 12 12, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 543-546 4 p. 6339375. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

研究成果: Conference contribution

4 引用 (Scopus)

Cool mega-array: A highly energy efficient reconfigurable accelerator

Ozaki, N., Yoshihiro, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011 12 1, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132668. (2011 International Conference on Field-Programmable Technology, FPT 2011).

研究成果: Conference contribution

13 引用 (Scopus)

Datapath generator based on gate-level symbolic layout

Matsumoto, N., Watanabe, Y., Usami, K., Sugeno, Y., Hatada, H. & Mori, S., 1990 1 1, 27th ACM/IEEE Design Automation Conference. Proceedings 1990. Publ by IEEE, p. 388-393 6 p. (27th ACM/IEEE Design Automation Conference. Proceedings 1990).

研究成果: Conference contribution

1 引用 (Scopus)

Delay modeling and static timing analysis for MTCMOS circuits

Ohkubo, N. & Usami, K., 2006 9 19, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. p. 570-575 6 p. 1594746. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 巻数 2006).

研究成果: Conference contribution

5 引用 (Scopus)

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors

Usami, K., Kudo, M., Matsunaga, K., Kosaka, T., Tsurui, Y., Wang, W., Amano, H., Kobayashi, H., Sakamoto, R., Namiki, M., Kondo, M. & Nakamura, H., 2014, 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings. p. 843-848 6 p. 6742995. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

9 引用 (Scopus)

Design and evaluation of fine-grained power-gating for embedded microprocessors

Kondo, M., Kobyashi, H., Sakamoto, R., Wada, M., Tsukamoto, J., Namiki, M., Wang, W., Amano, H., Matsunaga, K., Kudo, M., Usami, K., Komoda, T. & Nakamura, H., 2014 1 1, Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 6800359. (Proceedings -Design, Automation and Test in Europe, DATE).

研究成果: Conference contribution

14 引用 (Scopus)

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

Yoshida, Y. & Usami, K., 2017 6 29, Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 43-46 4 p. 7962596

研究成果: Conference contribution

1 引用 (Scopus)

Design and implementation of fine-grain power gating with ground bounce suppression

Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., Seki, N., Amano, H., Namiki, M., Imai, M., Kondo, M. & Nakamura, H., 2009 3 30, Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. p. 381-386 6 p. 4749703. (Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems).

研究成果: Conference contribution

25 引用 (Scopus)

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

Usami, K., Lgarashi, M., Ishikawa, T., Kanazawa, M., Takahashi, M., Hamada, M. & Arakida, H., 1998 1 1, Proceedings 1998 - Design and Automation Conference, DAC 1998. Institute of Electrical and Electronics Engineers Inc., p. 483-488 6 p. 724520. (Proceedings - Design Automation Conference).

研究成果: Conference contribution

29 引用 (Scopus)

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yoshida, Y., Usami, K. & Amano, H., 2018 5 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 148-149 2 p.

研究成果: Conference contribution

1 引用 (Scopus)

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

Koizumi, Y., Amano, H., Matsutani, H., Miura, N., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012 12 1, FPT 2012 - 2012 International Conference on Field-Programmable Technology. p. 293-296 4 p. 6412150. (FPT 2012 - 2012 International Conference on Field-Programmable Technology).

研究成果: Conference contribution

7 引用 (Scopus)

Dynamic VDD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

Yamamoto, T., Hironaka, K., Hayakawa, Y., Kimura, M., Amano, H. & Usami, K., 2011 4 4, Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Proceedings. p. 230-241 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 巻数 6578 LNCS).

研究成果: Conference contribution

9 引用 (Scopus)

Efficient leakage power saving by sleep depth controlling for multi-mode power gating

Takeda, S., Miwa, S., Usami, K. & Nakamura, H., 2012 7 16, Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012. p. 625-632 8 p. 6187558. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

研究成果: Conference contribution

4 引用 (Scopus)

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Usami, K., Akaike, J., Akiba, S., Kudo, M., Amano, H., Ikezoe, T., Hiraga, K., Shuto, Y. & Yagami, K., 2018 11 15, Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018. Institute of Electrical and Electronics Engineers Inc., p. 91-98 8 p. 8537701. (Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018).

研究成果: Conference contribution

2 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyamat, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2009 12 1, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. p. 281-284 4 p. 5357257. (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009).

研究成果: Conference contribution

33 引用 (Scopus)

Geyser-2: The second prototype CPU with fine-grained run-time power gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011 3 28, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. p. 87-88 2 p. 5722310. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

10 引用 (Scopus)

Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations

Shirai, T. & Usami, K., 2008 12 1, 2008 International SoC Design Conference, ISOCC 2008. p. I310-I313 4815634. (2008 International SoC Design Conference, ISOCC 2008; 巻数 1).

研究成果: Conference contribution

2 引用 (Scopus)

Implementation and evaluation of fine-grain run-time power gating for a multiplier

Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H. & Nakamura, H., 2009 12 1, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. p. 7-10 4 p. 5166253. (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009).

研究成果: Conference contribution

7 引用 (Scopus)

Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

Saito, Y., Shirai, T., Nakamura, T., Nishimura, T., Hasegawa, Y., Tsutsumi, S., Kashima, T., Nakata, M., Takeda, S., Usami, K. & Amano, H., 2008 12 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 329-332 4 p. 4762410. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

研究成果: Conference contribution

15 引用 (Scopus)

Level-shifter free approach for multi-Vdd SOTB employing adaptive Vt modulation for pMOSFET

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2018 3 7, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., 巻 2018-March. p. 1-3 3 p.

研究成果: Conference contribution

1 引用 (Scopus)

Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2017 12 13, 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 8203473

研究成果: Conference contribution

1 引用 (Scopus)

Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2019 1 1, VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Revised and Extended Selected Papers. Monteiro, J., Elfadel, I. A. M., Sonza Reorda, M., Ugurdag, H. F., Maniatakos, M. & Reis, R. (版). Springer New York LLC, p. 1-21 21 p. (IFIP Advances in Information and Communication Technology; 巻数 500).

研究成果: Conference contribution

Low-power design methodology and applications utilizing dual supply voltages

Usami, K. & Igarashi, M., 2000 12 1, Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000. p. 123-128 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

30 引用 (Scopus)

Measurement of the minimum energy point in Silicon on Thin-BOX(SOTB) and bulk MOSFET

Nakamura, S., Kawasaki, J., Kumagai, Y. & Usami, K., 2015 3 18, EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Institute of Electrical and Electronics Engineers Inc., p. 193-196 4 p. 7063746

研究成果: Conference contribution

12 引用 (Scopus)

Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

Usami, K., Akiba, S., Amano, H., Ikezoe, T., Hiraga, K., Suzuki, K. & Kanda, Y., 2020 4, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9097630. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings).

研究成果: Conference contribution

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor

Kudo, M. & Usami, K., 2017 10 10, NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium. Institute of Electrical and Electronics Engineers Inc., 8064472. (NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium).

研究成果: Conference contribution

1 引用 (Scopus)

On-chip detection methodology for break-even time of power gated function units

Usami, K., Goto, Y., Matsunaga, K., Koyama, S., Ikebuchi, D., Amano, H. & Nakamura, H., 2011 9 19, IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. p. 241-246 6 p. 5993643. (Proceedings of the International Symposium on Low Power Electronics and Design).

研究成果: Conference contribution

13 引用 (Scopus)

Overview on low power SoC design technology

Usami, K., 2007 12 1, Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. p. 634-636 3 p. 4196103. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

7 引用 (Scopus)

Power gating for FDSOI using dynamically body-biased power switch

Kumagai, Y., Kudo, M. & Usami, K., 2015 3 18, EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Institute of Electrical and Electronics Engineers Inc., p. 221-224 4 p. 7063813

研究成果: Conference contribution

Single Supply Level Shifter Circuit using body-bias

Takeyoshi, Y. & Usami, K., 2019 6, 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 8793384. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

研究成果: Conference contribution

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H. & Kondo, M., 2011 7 18, IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 5890918. (IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings).

研究成果: Conference contribution

2 引用 (Scopus)

Stepwise sleep depth control for run-time leakage power saving

Takeda, S., Miwa, S., Usami, K. & Nakamura, H., 2012 5 22, GLSVLSI'12 - Proceedings of the Great Lakes Symposium on VLSI 2012. p. 233-238 6 p. (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

研究成果: Conference contribution

2 引用 (Scopus)

Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Wang, W., Ohta, Y., Ishii, Y., Usami, K. & Amano, H., 2012 7 25, Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV. 6216587. (Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV).

研究成果: Conference contribution

4 引用 (Scopus)

Ultra fine-grained run-time power gating of on-chip routers for CMPs

Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2010 8 5, NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. p. 61-68 8 p. 5507560. (NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip).

研究成果: Conference contribution

46 引用 (Scopus)

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Kamohara, S., Sugii, N., Yamamoto, Y., Makiyama, H., Yamashita, T., Hasegawa, T., Okanishi, S., Yanagita, H., Kadoshima, M., Maekawa, K., Mitani, H., Yamagata, Y., Oda, H., Yamaguchi, Y., Ishibashi, K., Amano, H., Usami, K., Kobayashi, K., Mizutani, T. & Hiramoto, T., 2014 9 8, Digest of Technical Papers - Symposium on VLSI Technology. Institute of Electrical and Electronics Engineers Inc., 6894413. (Digest of Technical Papers - Symposium on VLSI Technology).

研究成果: Conference contribution

9 引用 (Scopus)

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating

Usami, K., Miyauchi, M., Kudo, M., Takagi, K., Amano, H., Namiki, M., Kondo, M. & Nakamura, H., 2014 12 2, 2014 International Symposium on System-on-Chip, SoC 2014. Daniel, O., Ellervee, P., Milojevic, D., Nurmi, J. & Paakki, T. (版). Institute of Electrical and Electronics Engineers Inc., 6972438. (2014 International Symposium on System-on-Chip, SoC 2014).

研究成果: Conference contribution

1 引用 (Scopus)
Editorial

Foreword: Special section on VLSI design and CAD algorithms

Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T. および17人, Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S. I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M. & Watanabe, T., 2014 12 1, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, 1 p.

研究成果: Editorial

Paper
65 引用 (Scopus)

Automated selective multi-threshold design for ultra-low standby applications

Usami, K., Kawabe, N., Koizumi, M., Seta, K. & Furusawa, T., 2002, p. 202-206. 5 p.

研究成果: Paper

60 引用 (Scopus)

Clock-gating method for low-power LSI design

Kitahara, T., Minami, F., Ueda, T., Usami, K., Nishio, S., Murakata, M. & Mitsuhashi, T., 1998 12 1, p. 307-312. 6 p.

研究成果: Paper

12 引用 (Scopus)