• 1613 引用
  • 20 h指数
1987 …2019

Research output per year

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

  • 1613 引用
  • 20 h指数
  • 68 Conference contribution
  • 36 Article
  • 1 Chapter
Conference contribution

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2016 5 24, 2013 IEEE Hot Chips 25 Symposium, HCS 2013. Institute of Electrical and Electronics Engineers Inc., 7478328

研究成果: Conference contribution

A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 6547916

研究成果: Conference contribution

1 引用 (Scopus)

A scheme to reduce active leakage power by detecting state transitions

Usami, K. & Yoshioka, H., 2004, Midwest Symposium on Circuits and Systems. 巻 1.

研究成果: Conference contribution

11 引用 (Scopus)

A thermal management system for building block computing systems

Fujita, Y., Usami, K. & Amano, H., 2014 11 6, Proceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014. Institute of Electrical and Electronics Engineers Inc., p. 165-171 7 p. 6949468

研究成果: Conference contribution

2 引用 (Scopus)

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Usami, K., Nogami, K., Igarashi, M., Minami, F., Kawasaki, Y., Ishikawa, T., Kanazawa, M., Aoki, T., Takano, M., Mizuno, C., Ichida, M., Sonoda, S., Takahashi, M. & Hatanaka, N., 1997, Proceedings of the Custom Integrated Circuits Conference. IEEE, p. 131-134 4 p.

研究成果: Conference contribution

22 引用 (Scopus)

Automated selective multi-threshold design for ultra-low standby applications

Usami, K., Kawabe, N., Koizumi, M., Seta, K. & Furusawa, T., 2002, Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers. p. 202-206 5 p.

研究成果: Conference contribution

60 引用 (Scopus)

Building block multi-chip systems using inductive coupling through chip interface

Amano, H., Kuroda, T., Nakamura, H., Usami, K., Kondo, M., Matsutani, H. & Namiki, M., 2018 5 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 152-154 3 p.

研究成果: Conference contribution

Clustered voltage scaling technique for low-power design

Usami, K. & Horowitz, M., 1995, Proceedings of the International Symposium on Low Power Design. New York, NY, United States: ACM, p. 3-8 6 p.

研究成果: Conference contribution

322 引用 (Scopus)

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect

Koizumi, Y., Sasaki, E., Amano, H., Matsutani, H., Take, Y., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 543-546 4 p. 6339375

研究成果: Conference contribution

3 引用 (Scopus)

Cool mega-array: A highly energy efficient reconfigurable accelerator

Ozaki, N., Yoshihiro, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132668

研究成果: Conference contribution

13 引用 (Scopus)

Datapath generator based on gate-level symbolic layout

Matsumoto, N., Watanabe, Y., Usami, K., Sugeno, Y., Hatada, H. & Mori, S., 1990, 27th ACM/IEEE Design Automation Conference. Proceedings 1990. Piscataway, NJ, United States: Publ by IEEE, p. 388-393 6 p.

研究成果: Conference contribution

1 引用 (Scopus)

Delay modeling and static timing analysis for MTCMOS circuits

Ohkubo, N. & Usami, K., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 巻 2006. p. 570-575 6 p. 1594746

研究成果: Conference contribution

5 引用 (Scopus)

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links

Koizumi, Y., Miura, N., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013, 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings. IEEE Computer Society, 6645628

研究成果: Conference contribution

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors

Usami, K., Kudo, M., Matsunaga, K., Kosaka, T., Tsurui, Y., Wang, W., Amano, H., Kobayashi, H., Sakamoto, R., Namiki, M., Kondo, M. & Nakamura, H., 2014, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 843-848 6 p. 6742995

研究成果: Conference contribution

9 引用 (Scopus)

Design and evaluation of fine-grained power-gating for embedded microprocessors

Kondo, M., Kobyashi, H., Sakamoto, R., Wada, M., Tsukamoto, J., Namiki, M., Wang, W., Amano, H., Matsunaga, K., Kudo, M., Usami, K., Komoda, T. & Nakamura, H., 2014, Proceedings -Design, Automation and Test in Europe, DATE. Institute of Electrical and Electronics Engineers Inc., 6800359

研究成果: Conference contribution

14 引用 (Scopus)

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

Yoshida, Y. & Usami, K., 2017 6 29, Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 43-46 4 p. 7962596

研究成果: Conference contribution

1 引用 (Scopus)

Design and implementation of fine-grain power gating with ground bounce suppression

Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., Seki, N., Amano, H., Namiki, M., Imai, M., Kondo, M. & Nakamura, H., 2009, Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. p. 381-386 6 p. 4749703

研究成果: Conference contribution

25 引用 (Scopus)

DESIGN METHODOLOGY OF STANDARD CELL LAYOUT AND PLA.

Usami, K., Ishii, A., Horie, A. & Iwamura, J., 1987, Proceedings of the Custom Integrated Circuits Conference. IEEE, p. 379-384 6 p.

研究成果: Conference contribution

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

Usami, K., Igarashi, M., Ishikawa, T., Kanazawa, M., Takahashi, M., Hamada, M., Arakida, H., Terazawa, T. & Kuroda, T., 1998, Proceedings - Design Automation Conference. IEEE, p. 483-488 6 p.

研究成果: Conference contribution

29 引用 (Scopus)

Design of a 32bit microprocessor, TX1

Tokumaru, T., Masuda, E., Hori, C., Usami, K., Miyata, M. & Iwamura, J., 1988, 1988 Symp VLSI Circuits Dig Tech Pap. Anon (版). p. 33-34 2 p.

研究成果: Conference contribution

4 引用 (Scopus)

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yoshida, Y., Usami, K. & Amano, H., 2018 5 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 148-149 2 p.

研究成果: Conference contribution

1 引用 (Scopus)

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

Koizumi, Y., Amano, H., Matsutani, H., Miura, N., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012, FPT 2012 - 2012 International Conference on Field-Programmable Technology. p. 293-296 4 p. 6412150

研究成果: Conference contribution

7 引用 (Scopus)

Dynamic VDD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

Yamamoto, T., Hironaka, K., Hayakawa, Y., Kimura, M., Amano, H. & Usami, K., 2011, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 巻 6578 LNCS. p. 230-241 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 巻数 6578 LNCS).

研究成果: Conference contribution

9 引用 (Scopus)

Efficient leakage power saving by sleep depth controlling for multi-mode power gating

Takeda, S., Miwa, S., Usami, K. & Nakamura, H., 2012, Proceedings - International Symposium on Quality Electronic Design, ISQED. p. 625-632 8 p. 6187558

研究成果: Conference contribution

4 引用 (Scopus)

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Usami, K., Akaike, J., Akiba, S., Kudo, M., Amano, H., Ikezoe, T., Hiraga, K., Shuto, Y. & Yagami, K., 2018 11 15, Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018. Institute of Electrical and Electronics Engineers Inc., p. 91-98 8 p. 8537701

研究成果: Conference contribution

1 引用 (Scopus)

Fine-grained power control using a multi-voltage variable pipeline router

Nakamura, T., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2012, Proceedings - IEEE 6th International Symposium on Embedded Multicore SoCs, MCSoC 2012. p. 59-66 8 p. 6354679

研究成果: Conference contribution

4 引用 (Scopus)

Function-level power estimation methodology for microprocessors

Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2000, Proceedings - Design Automation Conference. IEEE, p. 810-813 4 p.

研究成果: Conference contribution

66 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2010, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 369-370 2 p. 5419857

研究成果: Conference contribution

4 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyamat, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2009, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. p. 281-284 4 p. 5357257

研究成果: Conference contribution

33 引用 (Scopus)

Geyser-2: The second prototype CPU with fine-grained run-time power gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 87-88 2 p. 5722310

研究成果: Conference contribution

10 引用 (Scopus)

Hierarchical symbolic design methodology for large-scale datapaths

Usami, K., Sugeno, Y., Matsumoto, N. & Mori, S., 1990, Proceedings of the Custom Integrated Circuits Conference. Publ by IEEE

研究成果: Conference contribution

1 引用 (Scopus)

Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations

Shirai, T. & Usami, K., 2008, 2008 International SoC Design Conference, ISOCC 2008. 巻 1. 4815634

研究成果: Conference contribution

2 引用 (Scopus)

Implementation and evaluation of fine-grain run-time power gating for a multiplier

Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H. & Nakamura, H., 2009, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. p. 7-10 4 p. 5166253

研究成果: Conference contribution

7 引用 (Scopus)

Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

Saito, Y., Shirai, T., Nakamura, T., Nishimura, T., Hasegawa, Y., Tsutsumi, S., Kashima, T., Nakata, M., Takeda, S., Usami, K. & Amano, H., 2008, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 329-332 4 p. 4762410

研究成果: Conference contribution

15 引用 (Scopus)

Level-shifter free approach for multi-Vdd SOTB employing adaptive Vt modulation for pMOSFET

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2018 3 7, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., 巻 2018-March. p. 1-3 3 p.

研究成果: Conference contribution

1 引用 (Scopus)

Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2017 12 13, 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 8203473

研究成果: Conference contribution

1 引用 (Scopus)

Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2019 1 1, VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Revised and Extended Selected Papers. Monteiro, J., Elfadel, I. A. M., Sonza Reorda, M., Ugurdag, H. F., Maniatakos, M. & Reis, R. (版). Springer New York LLC, p. 1-21 21 p. (IFIP Advances in Information and Communication Technology; 巻数 500).

研究成果: Conference contribution

Low-power design methodology and applications utilizing dual supply voltages

Usami, K. & Igarashi, M., 2000, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 123-128 6 p.

研究成果: Conference contribution

30 引用 (Scopus)

Low-power design method using multiple supply voltages

Igarashi, M., Usami, K., Nogami, K., Minami, F., Kawasaki, Y., Aoki, T., Takano, M., Mizuno, C., Lshikawa, T., Kanazawa, M., Sonoda, S., Ichida, M. & Hatanaka, N., 1997, International Symposium on Low Power Electronics and Design, Digest of Technical Papers. Piscataway, NJ, United States: IEEE, p. 36-41 6 p.

研究成果: Conference contribution

51 引用 (Scopus)

Low-power design technique for ASICs by partially reducing supply voltage

Usami, K., Ishikawa, T., Kanazawa, M. & Kotani, H., 1996, Proceedings of the Annual IEEE International ASIC Conference and Exhibit. Meindl, J. D., Mukund, P. R., Gabara, T. & Sridhar, R. (版). p. 301-304 4 p.

研究成果: Conference contribution

24 引用 (Scopus)

Low-power technique for on-chip memory using biased partitioning and access concentration

Kawabe, N. & Usami, K., 2000, Proceedings of the Custom Integrated Circuits Conference. IEEE, p. 275-278 4 p.

研究成果: Conference contribution

6 引用 (Scopus)

Measurement of the minimum energy point in Silicon on Thin-BOX(SOTB) and bulk MOSFET

Nakamura, S., Kawasaki, J., Kumagai, Y. & Usami, K., 2015 3 18, EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Institute of Electrical and Electronics Engineers Inc., p. 193-196 4 p. 7063746

研究成果: Conference contribution

12 引用 (Scopus)

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor

Kudo, M. & Usami, K., 2017 10 10, NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium. Institute of Electrical and Electronics Engineers Inc., 8064472

研究成果: Conference contribution

1 引用 (Scopus)

On-chip detection methodology for break-even time of power gated function units

Usami, K., Goto, Y., Matsunaga, K., Koyama, S., Ikebuchi, D., Amano, H. & Nakamura, H., 2011, Proceedings of the International Symposium on Low Power Electronics and Design. p. 241-246 6 p. 5993643

研究成果: Conference contribution

13 引用 (Scopus)

Optimized design method for full-custom microprocessors

Usami, K. & Iwamura, J., 1989 5, Proceedings of the Custom Integrated Circuits Conference. Anon (版). Publ by IEEE

研究成果: Conference contribution

1 引用 (Scopus)

Overview on low power SoC design technology

Usami, K., 2007, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 634-636 3 p. 4196103

研究成果: Conference contribution

7 引用 (Scopus)

Power gating for FDSOI using dynamically body-biased power switch

Kumagai, Y., Kudo, M. & Usami, K., 2015 3 18, EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Institute of Electrical and Electronics Engineers Inc., p. 221-224 4 p. 7063813

研究成果: Conference contribution

Single Supply Level Shifter Circuit using body-bias

Takeyoshi, Y. & Usami, K., 2019 6 1, 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 8793384. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

研究成果: Conference contribution

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H. & Kondo, M., 2011, IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 5890918

研究成果: Conference contribution

2 引用 (Scopus)

Stepwise sleep depth control for run-time leakage power saving

Takeda, S., Miwa, S., Usami, K. & Nakamura, H., 2012, Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. p. 233-238 6 p.

研究成果: Conference contribution

2 引用 (Scopus)