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研究成果 1987 2019

  • 1588 引用
  • 19 h指数
  • 68 Conference contribution
  • 36 Article
  • 1 Chapter
フィルター
Conference contribution
2019

A coarse grained-reconfigurable accelerator with energy efficient MTJ-based non-volatile flip-flops

Ikezoe, T., Amano, H., Akaike, J., Usami, K., Kudo, M., Hiraga, K., Shuto, Y. & Yagami, K., 2019 2 13, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018. Andrews, D., Feregrino, C., Cumplido, R. & Stroobandt, D. (版). Institute of Electrical and Electronics Engineers Inc., 8641712. (2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018).

研究成果: Conference contribution

Flip flop circuits
Particle accelerators
Data storage equipment
Managers
Inventory control

Approximate Computing Technique Using Memoization and Simplified Multiplication

Ono, Y. & Usami, K., 2019 6 1, 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 8793369. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

研究成果: Conference contribution

Energy utilization
Embedded systems
Ion exchange

Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2019 1 1, VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Revised and Extended Selected Papers. Monteiro, J., Elfadel, I. A. M., Sonza Reorda, M., Ugurdag, H. F., Maniatakos, M. & Reis, R. (版). Springer New York LLC, p. 1-21 21 p. (IFIP Advances in Information and Communication Technology; 巻数 500).

研究成果: Conference contribution

Costs
Simulation
Temperature

Single Supply Level Shifter Circuit using body-bias

Takeyoshi, Y. & Usami, K., 2019 6 1, 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 8793384. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

研究成果: Conference contribution

Networks (circuits)
Electric potential
Energy utilization
Silicon
2018

Building block multi-chip systems using inductive coupling through chip interface

Amano, H., Kuroda, T., Nakamura, H., Usami, K., Kondo, M., Matsutani, H. & Namiki, M., 2018 5 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 152-154 3 p.

研究成果: Conference contribution

Computer operating systems
Network architecture
Interfaces (computer)
Networks (circuits)
Hot Temperature
1 引用 (Scopus)

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yoshida, Y., Usami, K. & Amano, H., 2018 5 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 148-149 2 p.

研究成果: Conference contribution

Data storage equipment
Macros
Computer peripheral equipment
Flip flop circuits
Static random access storage

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Usami, K., Akaike, J., Akiba, S., Kudo, M., Amano, H., Ikezoe, T., Hiraga, K., Shuto, Y. & Yagami, K., 2018 11 15, Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018. Institute of Electrical and Electronics Engineers Inc., p. 91-98 8 p. 8537701

研究成果: Conference contribution

Flip flop circuits
Sequential circuits
Energy dissipation
Durability
Image processing
1 引用 (Scopus)

Level-shifter free approach for multi-Vdd SOTB employing adaptive Vt modulation for pMOSFET

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2018 3 7, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., 巻 2018-March. p. 1-3 3 p.

研究成果: Conference contribution

Modulation
Silicon
Electric potential
Threshold voltage
Microprocessor chips
2017
1 引用 (Scopus)

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

Yoshida, Y. & Usami, K., 2017 6 29, Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 43-46 4 p. 7962596

研究成果: Conference contribution

Silicon
methodology
Data storage equipment
silicon
cells
1 引用 (Scopus)

Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2017 12 13, 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 8203473

研究成果: Conference contribution

Electric potential
Threshold voltage
Transistors
Modulation
Costs
1 引用 (Scopus)

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor

Kudo, M. & Usami, K., 2017 10 10, NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium. Institute of Electrical and Electronics Engineers Inc., 8064472

研究成果: Conference contribution

Tunnel junctions
Flip flop circuits
Microprocessor chips
Energy dissipation
Static random access storage
2016

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Kamohara, S., Sugii, N., Ishibashi, K., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2016 5 25, 2014 IEEE Hot Chips 26 Symposium, HCS 2014. Institute of Electrical and Electronics Engineers Inc., 7478838

研究成果: Conference contribution

Program processors
Sleep

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2016 5 24, 2013 IEEE Hot Chips 25 Symposium, HCS 2013. Institute of Electrical and Electronics Engineers Inc., 7478328

研究成果: Conference contribution

Particle accelerators
Reconfigurable architectures
Program processors
Scalability
Masks
2015

A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control

Okuhara, H., Usami, K. & Amano, H., 2015 7 14, IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVIII - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7158656

研究成果: Conference contribution

Bias voltage
Leakage currents
Detectors
Silicon
Networks (circuits)
12 引用 (Scopus)

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

Okuhara, H., Kitamori, K., Fujita, Y., Usami, K. & Amano, H., 2015 9 21, Proceedings of the International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 巻 2015-September. p. 207-212 6 p. 7273515

研究成果: Conference contribution

Bias voltage
Silicon
Controllers
Oxides
Electric potential
11 引用 (Scopus)

Measurement of the minimum energy point in Silicon on Thin-BOX(SOTB) and bulk MOSFET

Nakamura, S., Kawasaki, J., Kumagai, Y. & Usami, K., 2015 3 18, EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Institute of Electrical and Electronics Engineers Inc., p. 193-196 4 p. 7063746

研究成果: Conference contribution

Silicon
Logic circuits
Electric potential
Adders
Networks (circuits)

Power gating for FDSOI using dynamically body-biased power switch

Kumagai, Y., Kudo, M. & Usami, K., 2015 3 18, EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Institute of Electrical and Electronics Engineers Inc., p. 221-224 4 p. 7063813

研究成果: Conference contribution

Switches
Program processors
Threshold voltage
Application programs
Transistors
2014
19 引用 (Scopus)

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Ishibashi, K., Sugii, N., Usami, K., Amano, H., Kobayashi, K., Pham, C. K., Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Yamaguchi, Y., Oda, H., Hasegawa, T., Okanishi, S., Yanagita, H., Kamohara, S., Kadoshima, M., Maekawa, K., Yamashita, T., Le, D. H. および5人, Yomogita, T., Kudo, M., Kitamori, K., Kondo, S. & Manzawa, Y., 2014, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society, 6842954

研究成果: Conference contribution

Program processors
Silicon
Oxides
Sleep
2 引用 (Scopus)

A thermal management system for building block computing systems

Fujita, Y., Usami, K. & Amano, H., 2014 11 6, Proceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014. Institute of Electrical and Electronics Engineers Inc., p. 165-171 7 p. 6949468

研究成果: Conference contribution

Temperature control
Heat losses
Temperature
Temperature sensors
Voltage control
8 引用 (Scopus)

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors

Usami, K., Kudo, M., Matsunaga, K., Kosaka, T., Tsurui, Y., Wang, W., Amano, H., Kobayashi, H., Sakamoto, R., Namiki, M., Kondo, M. & Nakamura, H., 2014, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 843-848 6 p. 6742995

研究成果: Conference contribution

Microprocessor chips
Energy dissipation
Temperature
Sleep
13 引用 (Scopus)

Design and evaluation of fine-grained power-gating for embedded microprocessors

Kondo, M., Kobyashi, H., Sakamoto, R., Wada, M., Tsukamoto, J., Namiki, M., Wang, W., Amano, H., Matsunaga, K., Kudo, M., Usami, K., Komoda, T. & Nakamura, H., 2014, Proceedings -Design, Automation and Test in Europe, DATE. Institute of Electrical and Electronics Engineers Inc., 6800359

研究成果: Conference contribution

Microprocessor chips
Electric power utilization
Hardware
Leakage currents
Temperature
9 引用 (Scopus)

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Kamohara, S., Sugii, N., Yamamoto, Y., Makiyama, H., Yamashita, T., Hasegawa, T., Okanishi, S., Yanagita, H., Kadoshima, M., Maekawa, K., Mitani, H., Yamagata, Y., Oda, H., Yamaguchi, Y., Ishibashi, K., Amano, H., Usami, K., Kobayashi, K., Mizutani, T. & Hiramoto, T., 2014 9 8, Digest of Technical Papers - Symposium on VLSI Technology. Institute of Electrical and Electronics Engineers Inc., 6894413

研究成果: Conference contribution

Electronic equipment
Silicon
Oxides
Program processors
Electric potential
1 引用 (Scopus)

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating

Usami, K., Miyauchi, M., Kudo, M., Takagi, K., Amano, H., Namiki, M., Kondo, M. & Nakamura, H., 2014 12 2, 2014 International Symposium on System-on-Chip, SoC 2014. Institute of Electrical and Electronics Engineers Inc., 6972438

研究成果: Conference contribution

Microprocessor chips
Switches
Electric potential
2013

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533808

研究成果: Conference contribution

Electric potential
Energy conservation
Scheduling
High level synthesis
1 引用 (Scopus)

A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 6547916

研究成果: Conference contribution

Particle accelerators
Energy efficiency
Parallel processing systems
Program processors
Costs

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links

Koizumi, Y., Miura, N., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013, 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings. IEEE Computer Society, 6645628

研究成果: Conference contribution

Particle accelerators
Demonstrations
Electric potential
Program processors
Energy utilization
2012
14 引用 (Scopus)

A multi-Vdd dynamic variable-pipeline on-chip router for CMPs

Matsutani, H., Hirata, Y., Koibuchi, M., Usami, K., Nakamura, H. & Amano, H., 2012, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 407-412 6 p. 6164982

研究成果: Conference contribution

Routers
Pipelines
Electric potential
Electric power utilization
Simulators
3 引用 (Scopus)

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect

Koizumi, Y., Sasaki, E., Amano, H., Matsutani, H., Take, Y., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 543-546 4 p. 6339375

研究成果: Conference contribution

Particle accelerators
Combinatorial circuits
Packet switching
Packet networks
Switching networks
7 引用 (Scopus)

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

Koizumi, Y., Amano, H., Matsutani, H., Miura, N., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012, FPT 2012 - 2012 International Conference on Field-Programmable Technology. p. 293-296 4 p. 6412150

研究成果: Conference contribution

4 引用 (Scopus)

Efficient leakage power saving by sleep depth controlling for multi-mode power gating

Takeda, S., Miwa, S., Usami, K. & Nakamura, H., 2012, Proceedings - International Symposium on Quality Electronic Design, ISQED. p. 625-632 8 p. 6187558

研究成果: Conference contribution

Networks (circuits)
Electric potential
Sleep
Decision making
Temperature
4 引用 (Scopus)

Fine-grained power control using a multi-voltage variable pipeline router

Nakamura, T., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2012, Proceedings - IEEE 6th International Symposium on Embedded Multicore SoCs, MCSoC 2012. p. 59-66 8 p. 6354679

研究成果: Conference contribution

Routers
Power control
Pipelines
Electric potential
Voltage control
1 引用 (Scopus)

Stepwise sleep depth control for run-time leakage power saving

Takeda, S., Miwa, S., Usami, K. & Nakamura, H., 2012, Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. p. 233-238 6 p.

研究成果: Conference contribution

Sleep
Networks (circuits)
Temperature
4 引用 (Scopus)

Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Wang, W., Ohta, Y., Ishii, Y., Usami, K. & Amano, H., 2012, Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV. 6216587

研究成果: Conference contribution

Program processors
Costs
2011

A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS

Ozaki, N., Yasuda, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Symposium on Integrated Circuits, ISIC 2011. p. 579-584 6 p. 6131929

研究成果: Conference contribution

Combinatorial circuits
Particle accelerators
Processing
Data flow graphs
Data storage equipment
13 引用 (Scopus)

Cool mega-array: A highly energy efficient reconfigurable accelerator

Ozaki, N., Yoshihiro, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132668

研究成果: Conference contribution

Particle accelerators
Processing
Controllers
Information management
Electric power utilization
9 引用 (Scopus)

Dynamic VDD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

Yamamoto, T., Hironaka, K., Hayakawa, Y., Kimura, M., Amano, H. & Usami, K., 2011, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 巻 6578 LNCS. p. 230-241 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 巻数 6578 LNCS).

研究成果: Conference contribution

Energy dissipation
10 引用 (Scopus)

Geyser-2: The second prototype CPU with fine-grained run-time power gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 87-88 2 p. 5722310

研究成果: Conference contribution

Program processors
12 引用 (Scopus)

On-chip detection methodology for break-even time of power gated function units

Usami, K., Goto, Y., Matsunaga, K., Koyama, S., Ikebuchi, D., Amano, H. & Nakamura, H., 2011, Proceedings of the International Symposium on Low Power Electronics and Design. p. 241-246 6 p. 5993643

研究成果: Conference contribution

Program processors
Energy conservation
Switches
Networks (circuits)
Temperature
2 引用 (Scopus)

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H. & Kondo, M., 2011, IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 5890918

研究成果: Conference contribution

Particle accelerators
Combinatorial circuits
Processing
Clocks
Data storage equipment
2010
7 引用 (Scopus)

Adaptive power gating for function units in a microprocessor

Usami, K., Hashida, T., Koyama, S., Yamamoto, T., Ikebuchi, D., Amano, H., Namiki, M., Kondo, M. & Nakamura, H., 2010, Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010. p. 29-37 9 p. 5450407

研究成果: Conference contribution

Microprocessor chips
Energy conservation
Temperature
Limiters
Analytical models
4 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2010, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 369-370 2 p. 5419857

研究成果: Conference contribution

Program processors
40 引用 (Scopus)

Ultra fine-grained run-time power gating of on-chip routers for CMPs

Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2010, NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. p. 61-68 8 p. 5507560

研究成果: Conference contribution

Routers
Circuit simulation
2009
25 引用 (Scopus)

Design and implementation of fine-grain power gating with ground bounce suppression

Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., Seki, N., Amano, H., Namiki, M., Imai, M., Kondo, M. & Nakamura, H., 2009, Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. p. 381-386 6 p. 4749703

研究成果: Conference contribution

Switches
Program processors
Energy dissipation
Temperature
Sleep
32 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyamat, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2009, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. p. 281-284 4 p. 5357257

研究成果: Conference contribution

Program processors
Electric power utilization
7 引用 (Scopus)

Implementation and evaluation of fine-grain run-time power gating for a multiplier

Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H. & Nakamura, H., 2009, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. p. 7-10 4 p. 5166253

研究成果: Conference contribution

Energy conservation
Switches
Program processors
Analytical models
Energy dissipation
2008
34 引用 (Scopus)

A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

Seki, N., Zhao, L., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Toshihiro Kashima, K., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M. & Nakamura, H., 2008, 26th IEEE International Conference on Computer Design 2008, ICCD. p. 612-617 6 p. 4751924

研究成果: Conference contribution

Tapes
Pipelines
Sleep
2 引用 (Scopus)

Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations

Shirai, T. & Usami, K., 2008, 2008 International SoC Design Conference, ISOCC 2008. 巻 1. 4815634

研究成果: Conference contribution

Networks (circuits)
Simulated annealing
Degradation
14 引用 (Scopus)

Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

Saito, Y., Shirai, T., Nakamura, T., Nishimura, T., Hasegawa, Y., Tsutsumi, S., Kashima, T., Nakata, M., Takeda, S., Usami, K. & Amano, H., 2008, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 329-332 4 p. 4762410

研究成果: Conference contribution

Parallel processing systems
Electric power utilization
Clocks
Processing
2007
7 引用 (Scopus)

Overview on low power SoC design technology

Usami, K., 2007, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 634-636 3 p. 4196103

研究成果: Conference contribution

System-on-chip
2006
64 引用 (Scopus)

A design approach for fine-grained run-time power gating using locally extracted sleep signals

Usami, K. & Ohkubo, N., 2006, IEEE International Conference on Computer Design, ICCD 2006. p. 155-161 7 p. 4380809

研究成果: Conference contribution

Switches
Microprocessor chips
Clocks
Energy dissipation
Energy conservation