Pureに変更を加えた場合、すぐここに表示されます。

研究成果 1987 2019

  • 1588 引用
  • 19 h指数
  • 68 Conference contribution
  • 36 Article
  • 1 Chapter
フィルター
Article
2017
Data storage equipment
Silicon
Computer peripheral equipment
Flip flop circuits
Bias voltage
2016

An operating system guided fine-grained power gating control based on runtime characteristics of applications

Koshiba, A., Sato, M., Usami, K., Amano, H., Sakamoto, R., Kondo, M., Nakamura, H. & Namiki, M., 2016 8 1, : : IEICE Transactions on Electronics. E99C, 8, p. 926-935 10 p.

研究成果: Article

Electric power utilization
Application programs
Computer monitors
Networks (circuits)
2 引用 (Scopus)

Multi-voltage variable pipeline routers with the same clock frequency for low-power network-on-chips systems

Ahmed, A. B., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2016 8 1, : : IEICE Transactions on Electronics. E99C, 8, p. 909-917 9 p.

研究成果: Article

Routers
Clocks
Pipelines
Electric potential
Network-on-chip
9 引用 (Scopus)
Microcontrollers
Silicon
Bias voltage
Temperature
Electric potential
2015
2 引用 (Scopus)

A fine-grained power gating control on linux monitoring power consumption of processor functional units

Koshiba, A., Wada, M., Sakamoto, R., Sato, M., Kosaka, T., Usami, K., Amano, H., Kondo, M., Nakamura, H. & Namiki, M., 2015 7 1, : : IEICE Transactions on Electronics. E98C, 7, p. 559-568 10 p.

研究成果: Article

Electric power utilization
Monitoring
Electric potential
Microprocessor chips
Switches
1 引用 (Scopus)
Clocks
Energy conservation
Synchronization
Energy utilization
Communication
16 引用 (Scopus)

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Ishibashi, K., Sugii, N., Kamohara, S., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2015 7 1, : : IEICE Transactions on Electronics. E98C, 7, p. 536-543 8 p.

研究成果: Article

Program processors
Wearable computers
Harvesters
Energy harvesting
Silicon
2014

Foreword: Special section on VLSI design and CAD algorithms

Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T. および17人, Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S. I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M. & Watanabe, T., 2014 12 1, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2366 1 p.

研究成果: Article

2013
18 引用 (Scopus)

A scalable 3D heterogeneous multicore with an inductive ThruChip interface

Miura, N., Koizumi, Y., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 11, : : IEEE Micro. 33, 6, p. 6-15 10 p., 6684194.

研究成果: Article

Particle accelerators
Program processors
Costs
Energy utilization
Communication

Fine-grained run-tume power gating through co-optimization of circuit, architecture, and system software design

Nakamura, H., Wang, W., Ohta, Y., Usami, K., Amano, H., Kondo, M. & Namiki, M., 2013 4, : : IEICE Transactions on Electronics. E96-C, 4, p. 404-412 9 p.

研究成果: Article

Software design
Networks (circuits)
Electric power utilization
Power control
Geysers
2 引用 (Scopus)
Electric potential
High level synthesis
Energy conservation
Scheduling
2011
37 引用 (Scopus)

Cool mega-arrays: Ultralow-power reconfigurable accelerator chips

Ozaki, N., Yasuda, Y., Izawa, M., Saito, Y., Ikebuchi, D., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011 11, : : IEEE Micro. 31, 6, p. 6-18 13 p., 6060791.

研究成果: Article

Particle accelerators
Data flow graphs
Data storage equipment
Microcontrollers
Mobile devices
3 引用 (Scopus)

Design and implementation fine-grained power gating on microprocessor functional units

Lei, Z., Ikebuchi, D., Usami, K., Namiki, M., Kondo, M., Nakamura, H. & Amano, H., 2011, : : IPSJ Transactions on System LSI Design Methodology. 4, p. 182-192 11 p.

研究成果: Article

Microprocessor chips
Electric power utilization
10 引用 (Scopus)

Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011 1 26, : : 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011. p. 87-88

研究成果: Article

27 引用 (Scopus)

Performance, area, and power evaluations of ultrafine-grained run-time power-gating routers for CMPs

Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2011 4, : : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 4, p. 520-533 14 p., 5737865.

研究成果: Article

Routers
Application programs
Communication
1 引用 (Scopus)
Transistors
Networks (circuits)
Logic gates
Sleep
Degradation
4 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2010 1 18, : : Default journal. p. 369-370

研究成果: Article

2009
Controllers
Degradation
Networks (circuits)
32 引用 (Scopus)

Geyser-1: A MIPS R3000 CPU core with Fine Grain Runtime Power Gating

D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2009 11 16, : : IEEE Asian Solid-State Circuits Conference (A-SSCC) 2009. p. 281-284

研究成果: Article

Power Gating for Ultra-low Leakage: Physics; Design; and Analysis

F.Jerry, F. J., K.Choi, K. C., K.Usami, K. U. & Usami, K., 2008 3 3, : : Design; Automation and Test in Europe 2008 (DATE'08).

研究成果: Article

2006
Delay circuits
Networks (circuits)
Electric potential
SPICE
Interpolation

Leakage in Nanometer CMOS Technologies -Methodologies for Power Gating

Usami, K., Sakurai, T. & authors., . M., 2006 10 1, : : Default journal. p. 77-104

研究成果: Article

2005

Analysis on MTCMOS Circuits based on Lumped RC Model for Virtual Ground Line

K.Usami, K. U., N.Ohkubo, N. O., M.Shirakawa, M. S. & Usami, K., 2005 10 1, : : IEEE International SoC Design Conference 2005 (ISOCC'05). p. 116-119

研究成果: Article

2004
5 引用 (Scopus)
Finite automata
Transistors
Degradation
Combinatorial circuits
Logic gates
2002
4 引用 (Scopus)

Code coverage-based power estimation techniques for microprocessors

Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2002 10, : : Journal of Circuits, Systems and Computers. 11, 5, p. 557-574 18 p.

研究成果: Article

Microprocessor chips
Embedded software
Energy dissipation
Energy utilization
Simulators
1 引用 (Scopus)
Code division multiple access
Transistors
Sleep
1998
72 引用 (Scopus)

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Usami, K., Igarashi, M., Ishikawa, T., Kanazawa, M., Kuroda, T. & Furuyama, T., 1998 11, : : IEEE Journal of Solid-State Circuits. 33, 11, p. 1772-1778 7 p.

研究成果: Article

Energy dissipation
Static random access storage
Electric potential
Computer hardware
Decoding
191 引用 (Scopus)

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Usami, K., Igarashi, M., Minami, F., Ishikawa, T., Kanazawa, M., Ichida, M. & Nogami, K., 1998 3, : : IEEE Journal of Solid-State Circuits. 33, 3, p. 463-471 9 p.

研究成果: Article

Electric potential
Clocks
1991

Hierarchical symbolic design methodology for large-scale data paths

Usami, K., Sugeno, Y., Matsumoto, N. & Mori, S., 1991 3, : : IEEE Journal of Solid-State Circuits. 26, 3, p. 381-385 5 p.

研究成果: Article

Turnaround time
Adders
Microprocessor chips
Masks
Transistors
1989
1 引用 (Scopus)

Design of a 32-bit microprocessor, TX1

Tokumaru, T., Masuda, E., Usami, K., Usami, K., Miyata, M. & Iwamura, J., 1989 8, : : IEEE Journal of Solid-State Circuits. 24, 4, p. 938-944 7 p.

研究成果: Article

Microprocessor chips
Design for testability
Clocks
Transistors
Metals