0.1-μm p+-GaAs gate HJFET's fabricated using two-step dry-etching and selective MOMBE growth techniques

Shigeki Wada, Naoki Furuhata, Masatoshi Tokushima, Muneo Fukaishi, Hikaru Hida, Tadashi Maeda

研究成果: Article査読

2 被引用数 (Scopus)

抄録

This paper reports the first successful fabrication of high-performance, 0.1-μm p+-gate pseudomorphic heterojunction-FET's (HJFET's). By introducing the two-step dry-etching technique which compensates for the poor dry-etching resistance of PMMA, 0.1-jum or less gate-openings with a high aspect-ratio of 3.5 in SiO2 film are achieved. In addition, by using the gate-electrode filling technique with selective MOMBE p+-GaAs growth, 0.1-jum voidless p+-GaAs gate electrodes with a high aspect-ratio are achieved for the first time. The fabrication technology leads to a reduction of external gate fringing capacitance (Cfext) in a T-shaped gate-structure and an improvement in gate turn-on voltage. The fabricated 0.1-jum, T-shaped, p+-gate n-Al0.2Gao.sAs/In0 25Ga0.7sAs HJFET exhibits a high gate turn-on voltage (V>) of about 0.9 V, and a good gmmax of 435 mS/mm. Also, an excellent microwave performance of fT = 121 GHz and /max = 144 GHz is achieved due to the Cfext reduction. The technology and device show great promise for future high-speed applications, such as in power devices, MMIC's, and digital IC's.

本文言語English
ページ(範囲)1183-1189
ページ数7
ジャーナルIEEE Transactions on Electron Devices
45
6
DOI
出版ステータスPublished - 1998
外部発表はい

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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