0.2-μm Fully-Self-Aligned Y-Shaped Gate HJFET's with Reduced Gate-Fringing Capacitance Fabricated Using Collimated Sputtering and Electroless Au-Plating

Shigeki Wada, Masatoshi Tokushima, Muneo Fukaishi, Noriaki Matsuno, Hitoshi Yano, Hikaru Hida, Tadashi Maeda

研究成果: Article査読

7 被引用数 (Scopus)

抄録

This paper reports on new fully-self-aligned gate technology for 0.2-jum, high-aspect-ratio, Y-shaped-gate heterojunction-FET's (HJFET's) with about half the external gate-fringing capacitance (C f ext) of conventional Y-shaped gate HJFET's. The 0.2-jum Y-shaped gate openings are realized by anisotoropic dry-etching with stepper lithography and SiU2 sidewall techniques instead of electron beam lithography. By introducing WSi-collimated sputtering and electroless gold-plating techniques for the first time, we have developed a high-aspect-ratio, voidless and refractory Y-shaped gate-electrode without the need for mask alignments. A fabricated 0.2-jum gate n-Alo.2Gao.sAs/Ino.2Gao.sAs HJFET shows very small current saturation voltage of 0.25 V, marked gmmax of 631 mS/mm with 6-V gate-reverse breakdown voltage, and excellent threshold voltage uniformity of 9 mV. Also, the improved rf-performance such as /T -71 GHz and /max -120 GHz is realized even with the passivation for the high-aspect-ratio gate-structure with reduced CJxt. The developed technology based upon a fully-self-aligned and an all-dry-etching process provides higher performance and uniformity, thus it is very promising for high-speed and low-power-consumption digital and/or analog IC's/LSPs.

本文言語English
ページ(範囲)1656-1662
ページ数7
ジャーナルIEEE Transactions on Electron Devices
45
8
DOI
出版ステータスPublished - 1998
外部発表はい

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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