Ultra-low-power-consumption and high-speed DCFL circuits have been fabricated by using 0.2-/im Y-shaped gate E/D-heterojunction-FETs (HJFETs) with a high-aspectratio gate-structure, which has an advantage of reducing the gate-fringing capacitance (Cf) to about a half of that of a conventional low-aspect-ratio one. A fabricated 51-stage ring oscillator with the 0.2-/im Y-shaped gate n-AlGaAs/i-InGaAs E/DHJFETs shows the lowest power-delay product of 0.21 fj with an unloaded propagation delay of 34.9ps at a supply voltage (Vbo) of 0.4 V. We also analyze the DCFL switching characteristics by taking into account the intrinsic gate-to-source capacitance (Cj2') and the Cf. The analysis results for the power-delay products agree well with our experimental results. Our analysis also indicates the DCFL circuit with the high-aspcct-ratio Yshaped gate E/D-HJFETs can reduce the power-delay products by 35% or more below 0.25-/jm gate-length as compared to conventional ones with the low-aspect-ratio Y-shaped gate HJFETs. These results clarify that the Cf-reduction of the Y-shaped gate HJFETs is more effective in improving the power-delay products than reducing the gate-length.
|ジャーナル||IEICE Transactions on Electronics|
|出版ステータス||Published - 1999|
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