A new technology of fabricating 0.25 μm gate E/D-heterojunction FET LSIs is developed as a step towards the development of ultra low supply voltage LSIs. This technology, which is based upon all dry-process techniques, includes the formation of a 0.25 μm gate opening through the use of optical lithography and inner SiO2 sidewalls. The fmax and the gmmax for a Y-shaped gate E-HJFET are 108 GHz and 520 mS/mm, respectively. Excellent performances are obtained with DCFL ring oscillators using n-AlGaAs/i-InGaAs pseudomorphic E/D-HJFETs. These include 18 ps/G unloaded delay and 109 ps/G loaded delay (FI=FO=3, L=1mm) with 0.15 mW/G at a low supply voltage of 0.6 V, where inverters have a sufficient noise margin of more than 180 mV. Also, 10 Gbps error-free operation of a selector switch is demonstrated with 9.4 mW at 0.6 V.