110Gb/s multiplexing and demultiplexing ICs

Yasuyuki Suzuki, Yasushi Amamiya, Zin Yamazaki, Shigeki Wada, Hiroaki Uchida, Chiharu Kurioka, Shinichi Tanaka, Hikaru Hida

研究成果: Conference article

4 引用 (Scopus)

抜粋

A 120Gb/s multiplexer and a 110Gb/s demultiplexer are implemented in an InP HBT process. They feature a direct drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted micro-strip lines. Their input sensitivity is less than 100mVpp, and the output swing is more than 400mVpp.

元の言語English
ページ(範囲)182-183+518
ジャーナルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
47
出版物ステータスPublished - 2003 12 1
外部発表Yes
イベントDigest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement - San Francisco, CA., United States
継続期間: 2003 2 152003 2 19

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • これを引用

    Suzuki, Y., Amamiya, Y., Yamazaki, Z., Wada, S., Uchida, H., Kurioka, C., Tanaka, S., & Hida, H. (2003). 110Gb/s multiplexing and demultiplexing ICs. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 47, 182-183+518.