120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs

Yasuyuki Suzuki; Zin Yamazaki; Yasushi Amamiya; Shigeki Wada; Hiroaki Uchida; Chiharu Kurioka; Shinichi Tanaka; Hikaru Hida

doi:10.1109/JSSC.2004.835647

120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs

Yasuyuki Suzuki, Zin Yamazaki, Yasushi Amamiya, Shigeki Wada, Hiroaki Uchida, Chiharu Kurioka, Shinichi Tanaka, Hikaru Hida

研究成果: Article › 査読

47 被引用数 (Scopus)

抄録

InP HBT ICs capable of 120-Gb/s multiplexing and 110-Gb/s demultiplexing operation have been developed. They feature a direct-drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted microstrip lines. Their input sensitivity is less than 100 mV_pp, and the output swing is more than 400 mV _pp. To the best of our knowledge, this result is the highest data rate operation reported for electronic ICs. Moreover, error-free multiplexing and demultiplexing operation at 100 Gb/s was demonstrated.

本文言語	English
ページ（範囲）	2397-2402
ページ数	6
ジャーナル	IEEE Journal of Solid-State Circuits
巻	39
号	12
DOI	https://doi.org/10.1109/JSSC.2004.835647
出版ステータス	Published - 2004 12 1
外部発表	はい

ASJC Scopus subject areas

Electrical and Electronic Engineering

文献へのアクセス

10.1109/JSSC.2004.835647

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引用スタイル

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AU - Uchida, Hiroaki

AU - Kurioka, Chiharu

AU - Tanaka, Shinichi

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