120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs

Yasuyuki Suzuki, Zin Yamazaki, Yasushi Amamiya, Shigeki Wada, Hiroaki Uchida, Chiharu Kurioka, Shinichi Tanaka, Hikaru Hida

研究成果: Article

47 引用 (Scopus)

抜粋

InP HBT ICs capable of 120-Gb/s multiplexing and 110-Gb/s demultiplexing operation have been developed. They feature a direct-drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted microstrip lines. Their input sensitivity is less than 100 mVpp, and the output swing is more than 400 mV pp. To the best of our knowledge, this result is the highest data rate operation reported for electronic ICs. Moreover, error-free multiplexing and demultiplexing operation at 100 Gb/s was demonstrated.

元の言語English
ページ(範囲)2397-2402
ページ数6
ジャーナルIEEE Journal of Solid-State Circuits
39
発行部数12
DOI
出版物ステータスPublished - 2004 12 1
外部発表Yes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Suzuki, Y., Yamazaki, Z., Amamiya, Y., Wada, S., Uchida, H., Kurioka, C., Tanaka, S., & Hida, H. (2004). 120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs. IEEE Journal of Solid-State Circuits, 39(12), 2397-2402. https://doi.org/10.1109/JSSC.2004.835647