This paper reports the first low (1.5-V) supply voltage D-F/F able to run at a full rate of over 43 Gb/s. The proposed F/F circuitry incorporates parallel current switching together with inductive peaking, a combination that makes it suitable for over-43-Gb/s operation at a supply voltage as low as 1.5 V. The D-F/F, implemented through an InP-HBT process, provided 43-Gb/s error free operation with a large clock phase margin of 232 degrees. Moreover, the D-F/F produced a well-opened 50-Gb/s eye diagram. Power dissipation (Pdiss) of the D-F/F core circuit was reduced to 40 mW, which is less than one-tenth that of our conventional D-F/F. The F/F circuitry should help enable development of a low-Pdiss 43-Gb/s full-rate module with a 1.5-V-range supply voltage, which can be seamlessly connected with high-speed CMOS I/O circuits.
|出版ステータス||Published - 2003|
|イベント||GaAs IC Symposium IEEE Gallium Arsenide Intergrated Circuit Symposium - San Diego, CA, United States|
継続期間: 2003 11月 9 → 2003 11月 12
|Conference||GaAs IC Symposium IEEE Gallium Arsenide Intergrated Circuit Symposium|
|City||San Diego, CA|
|Period||03/11/9 → 03/11/12|
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