1.5-V low supply voltage 43-Gb/s delayed flip-flop circuit

Yasushi Amamiya, Yasuyuki Suzuki, Jin Yamazaki, Akira Fujihara, Shinichi Tanaka, Hikaru Hida

研究成果: Paper

15 引用 (Scopus)

抜粋

This paper reports the first low (1.5-V) supply voltage D-F/F able to run at a full rate of over 43 Gb/s. The proposed F/F circuitry incorporates parallel current switching together with inductive peaking, a combination that makes it suitable for over-43-Gb/s operation at a supply voltage as low as 1.5 V. The D-F/F, implemented through an InP-HBT process, provided 43-Gb/s error free operation with a large clock phase margin of 232 degrees. Moreover, the D-F/F produced a well-opened 50-Gb/s eye diagram. Power dissipation (Pdiss) of the D-F/F core circuit was reduced to 40 mW, which is less than one-tenth that of our conventional D-F/F. The F/F circuitry should help enable development of a low-Pdiss 43-Gb/s full-rate module with a 1.5-V-range supply voltage, which can be seamlessly connected with high-speed CMOS I/O circuits.

元の言語English
ページ169-172
ページ数4
DOI
出版物ステータスPublished - 2003
イベントGaAs IC Symposium IEEE Gallium Arsenide Intergrated Circuit Symposium - San Diego, CA, United States
継続期間: 2003 11 92003 11 12

Conference

ConferenceGaAs IC Symposium IEEE Gallium Arsenide Intergrated Circuit Symposium
United States
San Diego, CA
期間03/11/903/11/12

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Amamiya, Y., Suzuki, Y., Yamazaki, J., Fujihara, A., Tanaka, S., & Hida, H. (2003). 1.5-V low supply voltage 43-Gb/s delayed flip-flop circuit. 169-172. 論文発表場所 GaAs IC Symposium IEEE Gallium Arsenide Intergrated Circuit Symposium, San Diego, CA, United States. https://doi.org/10.1109/gaas.2003.1252387