A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps

Masahiro Fujii, Tadashi Maeda, Yasuo Ohno

研究成果: Article

1 被引用数 (Scopus)

抄録

A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0. 25 μm n-AlGaAs/i-InGaAs HJFET process operates at up to lOGbps with power consumption as low as 19 mW at a supply voltage of 1. 3 V.

本文言語English
ページ(範囲)512-516
ページ数5
ジャーナルIEICE Transactions on Electronics
E79-C
4
出版ステータスPublished - 1996 1 1
外部発表はい

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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