A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps

Masahiro Fujii; Tadashi Maeda; Yasuo Ohno

A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps

Masahiro Fujii, Tadashi Maeda, Yasuo Ohno

研究成果: Article › 査読

抄録

A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average g_m within the swing. An SCFL D-FF fabricated using a 0. 25 μm n-AlGaAs/i-InGaAs HJFET process operates at up to lOGbps with power consumption as low as 19 mW at a supply voltage of 1. 3 V.

本文言語	English
ページ（範囲）	512-516
ページ数	5
ジャーナル	IEICE Transactions on Electronics
巻	E79-C
号	4
出版ステータス	Published - 1996
外部発表	はい

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
電子工学および電気工学

他のファイルとリンク

引用スタイル

@article{2715015e421a419a9273368046d2bfe0,

title = "A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps",

abstract = "A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0. 25 μm n-AlGaAs/i-InGaAs HJFET process operates at up to lOGbps with power consumption as low as 19 mW at a supply voltage of 1. 3 V.",

keywords = "D-FF, Gaas, Heterojunction fet, High speed, Logic swing, Low power, Low supply voltage, SCFL",

author = "Masahiro Fujii and Tadashi Maeda and Yasuo Ohno",

year = "1996",

language = "English",

volume = "E79-C",

pages = "512--516",

journal = "IEICE Transactions on Electronics",

issn = "0916-8524",

publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",

number = "4",

}

TY - JOUR

T1 - A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps

AU - Fujii, Masahiro

AU - Maeda, Tadashi

AU - Ohno, Yasuo

PY - 1996

Y1 - 1996

N2 - A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0. 25 μm n-AlGaAs/i-InGaAs HJFET process operates at up to lOGbps with power consumption as low as 19 mW at a supply voltage of 1. 3 V.

AB - A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0. 25 μm n-AlGaAs/i-InGaAs HJFET process operates at up to lOGbps with power consumption as low as 19 mW at a supply voltage of 1. 3 V.

KW - D-FF

KW - Gaas

KW - Heterojunction fet

KW - High speed

KW - Logic swing

KW - Low power

KW - Low supply voltage

KW - SCFL

UR - http://www.scopus.com/inward/record.url?scp=0030125255&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030125255&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0030125255

VL - E79-C

SP - 512

EP - 516

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 4

ER -

A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps

抄録

ASJC Scopus subject areas

他のファイルとリンク

フィンガープリント

引用スタイル