A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC

Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi

研究成果: Conference contribution

21 引用 (Scopus)

抜粋

All-digital phase-locked loops (ADPLLs) offer the advantages of eliminating the large on-chip passive filter and not suffering from poor low-supply-voltage operation with process scaling [1,2]. However, there is a challenge in achieving low power consumption at the same time as providing the low phase noise required in modern wireless systems like WiFi and WiMAX that have higher-order modulations. Recently, efforts improve phase noise have been accomplished by increasing the time resolution of the time-to-digital converter (TDC) using a gated ring-oscillator structure by using a multipath ring oscillator [3], 2-step structures based on a vernier delay line [4] or a time-amplifier [5,6]. However, these structures require large power consumption because they require many continuously operating high-speed delay-stages.

元の言語English
ホスト出版物のタイトル2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
ページ470-471
ページ数2
DOI
出版物ステータスPublished - 2010 5 18
外部発表Yes
イベント2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, CA, United States
継続期間: 2010 2 72010 2 11

出版物シリーズ

名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
53
ISSN(印刷物)0193-6530

Other

Other2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
United States
San Francisco, CA
期間10/2/710/2/11

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • これを引用

    Tokairin, T., Okada, M., Kitsunezuka, M., Maeda, T., & Fukaishi, M. (2010). A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. : 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers (pp. 470-471). [5433843] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; 巻数 53). https://doi.org/10.1109/ISSCC.2010.5433843