A 3.5mm2, inductor-less digital-intensive radio SoC for 300-to-950MHz ISM-band applications supporting 1.0-to-240kbps multi-data-rates

Takashi Tokairin, Hiromi Saito, Haruya Ishizaki, Yoshitaka Oka, Tadashi Maeda, Seiichi Oshima, Masaaki Soda, Mitsuji Okada, Shinichi Hori, Masaki Kitsunezuka, Masayuki Mizuno

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

A small-sized (less than 2mm2 total analog and radio area) sub-GHz radio SoC for low power and low data-rate wireless applications is presented. The SoC has been equipped with a low-power analog-to-digital conversion scheme having a variable over-sampling ratio, multi-sampling-rate channel select filtering, and inductor-less RF front-end circuits incorporating a high output power stair-like shaping CMOS power-amplifier with a duty-imbalance-compensated level-shifter. The SoC, fabricated with 90nm CMOS, occupies only 3.5mm2. It has a sensitivity of -118dBm in a 2.4kbps FSK mode for a 433MHz band, and channel selectivity for data rates ranging from 1.0 to 240kbps.

本文言語English
ホスト出版物のタイトル2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
ページ30-31
ページ数2
出版ステータスPublished - 2011 9 16
外部発表はい
イベント2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan
継続期間: 2011 6 152011 6 17

出版物シリーズ

名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2011 Symposium on VLSI Circuits, VLSIC 2011
CountryJapan
CityKyoto
Period11/6/1511/6/17

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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