A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Tetsuya Fujita, Fumitoshi Hatori, Shinji Mita, Kojiro Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Tadahiro Kuroda, Tohru Furuyama

研究成果: Article

72 引用 (Scopus)

抄録

A 60-mW MPEG4 video codec has been developed for mobile multimedia applications. This codec supports both the H.263 ITU-T recommendation and the simple profile of MPEG4 committee draft version 1 released in November 1997. It is composed of a 16-bit reduced instruction set computer processor and several dedicated hardware engines so as to satisfy both power efficiency and programmability. It performs 10 frames/s of encoding and decoding with quarter-common intermediate format at 30 MHz. Several innovative low-power techniques were employed in both architectural and circuit levels, and the final power dissipation is 60 mW at 30 MHz, which is only 30% of the power dissipation for a conventional CMOS design. The chip was fabricated in a 0.3-μ m CMOS with double-well and triplemetal technology. It contains 3 million transistors, including a 52-kB on-chip SRAM. Internal supply voltages of 2.5 and 1.75 V are generated by on-chip dc-dc converters from 3.3-V external supply voltage.

元の言語English
ページ(範囲)1772-1778
ページ数7
ジャーナルIEEE Journal of Solid-State Circuits
33
発行部数11
DOI
出版物ステータスPublished - 1998 11
外部発表Yes

Fingerprint

Energy dissipation
Static random access storage
Electric potential
Computer hardware
Decoding
Transistors
Engines
Networks (circuits)
Voltage scaling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Fujita, T., Hatori, F., ... Furuyama, T. (1998). A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. IEEE Journal of Solid-State Circuits, 33(11), 1772-1778. https://doi.org/10.1109/4.726575

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. / Takahashi, Masafumi; Hamada, Mototsugu; Nishikawa, Tsuyoshi; Arakida, Hideho; Fujita, Tetsuya; Hatori, Fumitoshi; Mita, Shinji; Suzuki, Kojiro; Chiba, Akihiko; Terazawa, Toshihiro; Sano, Fumihiko; Watanabe, Yoshinori; Usami, Kimiyoshi; Igarashi, Mutsunori; Ishikawa, Takashi; Kanazawa, Masahiro; Kuroda, Tadahiro; Furuyama, Tohru.

:: IEEE Journal of Solid-State Circuits, 巻 33, 番号 11, 11.1998, p. 1772-1778.

研究成果: Article

Takahashi, M, Hamada, M, Nishikawa, T, Arakida, H, Fujita, T, Hatori, F, Mita, S, Suzuki, K, Chiba, A, Terazawa, T, Sano, F, Watanabe, Y, Usami, K, Igarashi, M, Ishikawa, T, Kanazawa, M, Kuroda, T & Furuyama, T 1998, 'A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme', IEEE Journal of Solid-State Circuits, 巻. 33, 番号 11, pp. 1772-1778. https://doi.org/10.1109/4.726575
Takahashi, Masafumi ; Hamada, Mototsugu ; Nishikawa, Tsuyoshi ; Arakida, Hideho ; Fujita, Tetsuya ; Hatori, Fumitoshi ; Mita, Shinji ; Suzuki, Kojiro ; Chiba, Akihiko ; Terazawa, Toshihiro ; Sano, Fumihiko ; Watanabe, Yoshinori ; Usami, Kimiyoshi ; Igarashi, Mutsunori ; Ishikawa, Takashi ; Kanazawa, Masahiro ; Kuroda, Tadahiro ; Furuyama, Tohru. / A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. :: IEEE Journal of Solid-State Circuits. 1998 ; 巻 33, 番号 11. pp. 1772-1778.
@article{3351b7379d974ef5b60a75192f9a0484,
title = "A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme",
abstract = "A 60-mW MPEG4 video codec has been developed for mobile multimedia applications. This codec supports both the H.263 ITU-T recommendation and the simple profile of MPEG4 committee draft version 1 released in November 1997. It is composed of a 16-bit reduced instruction set computer processor and several dedicated hardware engines so as to satisfy both power efficiency and programmability. It performs 10 frames/s of encoding and decoding with quarter-common intermediate format at 30 MHz. Several innovative low-power techniques were employed in both architectural and circuit levels, and the final power dissipation is 60 mW at 30 MHz, which is only 30{\%} of the power dissipation for a conventional CMOS design. The chip was fabricated in a 0.3-μ m CMOS with double-well and triplemetal technology. It contains 3 million transistors, including a 52-kB on-chip SRAM. Internal supply voltages of 2.5 and 1.75 V are generated by on-chip dc-dc converters from 3.3-V external supply voltage.",
keywords = "Clock gating, CVS, Low power, MPEG4, Pipelining, Video codec, VS, VT-CMOS",
author = "Masafumi Takahashi and Mototsugu Hamada and Tsuyoshi Nishikawa and Hideho Arakida and Tetsuya Fujita and Fumitoshi Hatori and Shinji Mita and Kojiro Suzuki and Akihiko Chiba and Toshihiro Terazawa and Fumihiko Sano and Yoshinori Watanabe and Kimiyoshi Usami and Mutsunori Igarashi and Takashi Ishikawa and Masahiro Kanazawa and Tadahiro Kuroda and Tohru Furuyama",
year = "1998",
month = "11",
doi = "10.1109/4.726575",
language = "English",
volume = "33",
pages = "1772--1778",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "11",

}

TY - JOUR

T1 - A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

AU - Takahashi, Masafumi

AU - Hamada, Mototsugu

AU - Nishikawa, Tsuyoshi

AU - Arakida, Hideho

AU - Fujita, Tetsuya

AU - Hatori, Fumitoshi

AU - Mita, Shinji

AU - Suzuki, Kojiro

AU - Chiba, Akihiko

AU - Terazawa, Toshihiro

AU - Sano, Fumihiko

AU - Watanabe, Yoshinori

AU - Usami, Kimiyoshi

AU - Igarashi, Mutsunori

AU - Ishikawa, Takashi

AU - Kanazawa, Masahiro

AU - Kuroda, Tadahiro

AU - Furuyama, Tohru

PY - 1998/11

Y1 - 1998/11

N2 - A 60-mW MPEG4 video codec has been developed for mobile multimedia applications. This codec supports both the H.263 ITU-T recommendation and the simple profile of MPEG4 committee draft version 1 released in November 1997. It is composed of a 16-bit reduced instruction set computer processor and several dedicated hardware engines so as to satisfy both power efficiency and programmability. It performs 10 frames/s of encoding and decoding with quarter-common intermediate format at 30 MHz. Several innovative low-power techniques were employed in both architectural and circuit levels, and the final power dissipation is 60 mW at 30 MHz, which is only 30% of the power dissipation for a conventional CMOS design. The chip was fabricated in a 0.3-μ m CMOS with double-well and triplemetal technology. It contains 3 million transistors, including a 52-kB on-chip SRAM. Internal supply voltages of 2.5 and 1.75 V are generated by on-chip dc-dc converters from 3.3-V external supply voltage.

AB - A 60-mW MPEG4 video codec has been developed for mobile multimedia applications. This codec supports both the H.263 ITU-T recommendation and the simple profile of MPEG4 committee draft version 1 released in November 1997. It is composed of a 16-bit reduced instruction set computer processor and several dedicated hardware engines so as to satisfy both power efficiency and programmability. It performs 10 frames/s of encoding and decoding with quarter-common intermediate format at 30 MHz. Several innovative low-power techniques were employed in both architectural and circuit levels, and the final power dissipation is 60 mW at 30 MHz, which is only 30% of the power dissipation for a conventional CMOS design. The chip was fabricated in a 0.3-μ m CMOS with double-well and triplemetal technology. It contains 3 million transistors, including a 52-kB on-chip SRAM. Internal supply voltages of 2.5 and 1.75 V are generated by on-chip dc-dc converters from 3.3-V external supply voltage.

KW - Clock gating

KW - CVS

KW - Low power

KW - MPEG4

KW - Pipelining

KW - Video codec

KW - VS

KW - VT-CMOS

UR - http://www.scopus.com/inward/record.url?scp=0032205691&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032205691&partnerID=8YFLogxK

U2 - 10.1109/4.726575

DO - 10.1109/4.726575

M3 - Article

AN - SCOPUS:0032205691

VL - 33

SP - 1772

EP - 1778

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 11

ER -