A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's

Tadashi Maeda, Keiichi Numata, Masatoshi Tokushima, Masaoki Ishikawa, Muneo Fukaishi, Hikaru Hida, Yasuo Ohno

研究成果: Article査読

4 被引用数 (Scopus)

抄録

This paper describes a low-supply-voltage flip flop circuit design. The advantages of low supply voltage are discussed. Based on an analytical circuit delay model, conventional flip flop operating speed degradation below 1 V supply voltage is analyzed. We then propose a new GaAs static flip flop, called TD-FF (tri-state driver flip-flop), for ultra-low supply voltage GaAs heterojunction FET LSI's. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage. The 10 Gbps power consumption is 1/5 of the minimum value reported for D-FF's so far. We also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.

本文言語English
ページ(範囲)240-246
ページ数7
ジャーナルIEEE Journal of Solid-State Circuits
31
2
DOI
出版ステータスPublished - 1996 2
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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