抄録
Based on a cascode-driver source-follower buffer, and a passive sampling architecture, we have implemented a differential sample-and-hold circuit in a 0.8 μm digital CMOS process. The buffer which eliminates channel length modulation of the driver device behaves very linearly, in low frequencies or sampled-data applications. This is the main reason that this first open-loop CMOS sample-and-hold can achieves very high linearity while functions at very high sampling rate. The circuit achieved -61 dB THD for a 1.42 Vp-p 10 MHz input signal at a 103 MHz sampling rate and -55.9 dB THD for a 1.22 Vp-p 20 MHz at a 101 MHz sampling rate.
本文言語 | English |
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ページ(範囲) | 261-266 |
ページ数 | 6 |
ジャーナル | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
巻 | E82-A |
号 | 2 |
出版ステータス | Published - 2000 1月 1 |
外部発表 | はい |
ASJC Scopus subject areas
- 信号処理
- コンピュータ グラフィックスおよびコンピュータ支援設計
- 電子工学および電気工学
- 応用数学