抄録
Based on a cascode-driver source-follower buffer, and a passive sampling architecture, we have implemented a differential sample-and-hold circuit in a 0.8 μm digital CMOS process. The buffer which eliminates channel length modulation of the driver device behaves very linearly, in low frequencies or sampled-data applications. This is the main reason that this first open-loop CMOS sample-and-hold can achieves very high linearity while functions at very high sampling rate. The circuit achieved -61 dB THD for a 1.42 Vp-p 10 MHz input signal at a 103 MHz sampling rate and -55.9 dB THD for a 1.22 Vp-p 20 MHz at a 101 MHz sampling rate.
| 元の言語 | English |
|---|---|
| ページ（範囲） | 261-266 |
| ページ数 | 6 |
| ジャーナル | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| 巻 | E82-A |
| 発行部数 | 2 |
| 出版物ステータス | Published - 2000 |
| 外部発表 | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture
- Information Systems
これを引用
A highly linear open-loop full CMOS high-speed sample-and-hold stage. / Hadidi, Khayrollah; Sasaki, Masahiro; Watanabe, Tadatoshi; Muramatsu, Daigo; Matsumoto, Takashi.
：: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 巻 E82-A, 番号 2, 2000, p. 261-266.研究成果: Article
}
TY - JOUR
T1 - A highly linear open-loop full CMOS high-speed sample-and-hold stage
AU - Hadidi, Khayrollah
AU - Sasaki, Masahiro
AU - Watanabe, Tadatoshi
AU - Muramatsu, Daigo
AU - Matsumoto, Takashi
PY - 2000
Y1 - 2000
N2 - Based on a cascode-driver source-follower buffer, and a passive sampling architecture, we have implemented a differential sample-and-hold circuit in a 0.8 μm digital CMOS process. The buffer which eliminates channel length modulation of the driver device behaves very linearly, in low frequencies or sampled-data applications. This is the main reason that this first open-loop CMOS sample-and-hold can achieves very high linearity while functions at very high sampling rate. The circuit achieved -61 dB THD for a 1.42 Vp-p 10 MHz input signal at a 103 MHz sampling rate and -55.9 dB THD for a 1.22 Vp-p 20 MHz at a 101 MHz sampling rate.
AB - Based on a cascode-driver source-follower buffer, and a passive sampling architecture, we have implemented a differential sample-and-hold circuit in a 0.8 μm digital CMOS process. The buffer which eliminates channel length modulation of the driver device behaves very linearly, in low frequencies or sampled-data applications. This is the main reason that this first open-loop CMOS sample-and-hold can achieves very high linearity while functions at very high sampling rate. The circuit achieved -61 dB THD for a 1.42 Vp-p 10 MHz input signal at a 103 MHz sampling rate and -55.9 dB THD for a 1.22 Vp-p 20 MHz at a 101 MHz sampling rate.
KW - CMOS buffers
KW - Full CMOS S/H
KW - Open-loop S/H
KW - S/H
KW - Sample-and-hold
UR - http://www.scopus.com/inward/record.url?scp=0033889428&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0033889428&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0033889428
VL - E82-A
SP - 261
EP - 266
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 2
ER -