A logarithmic compression ADC using transient response of a comparator

Yuji Inagaki, Yusaku Sugimori, Eri Ioka, Yasuyuki Matsuya

研究成果: Research - 審査Article

抄録

This paper describes a logarithmic compression ADC using a subranging TDC and the transient response of a comparator. We utilized the settling time of the comparator for a logarithmic compression instead of a logarithmic amplifier. The settling time of the comparator is inversely proportional to the logarithm of an input voltage. In the proposed ADC, an input voltage is converted into a pulse whose width represents the settling time of the comparator. Subsequently, the TDC converts the pulse width into a binary code. The supply voltage of the proposed ADC can be reduced more than a conventional logarithmic ADC because an analog to digital conversion takes place in the time domain. We confirmed through a 0.18-μm CMOS circuit simulation that the proposed ADC achieves a resolution of 11 bits, a sampling rate of 20 MS/s, a dynamic range of 59 dB and a power consumption of 9.8 mW at 1.5 V operation.

言語English
ページ359-362
Number of pages4
ジャーナルIEICE Transactions on Electronics
VolumeE100C
4
DOIs
StatePublished - 2017 4 1
外部発表Yes

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Transient analysis
Electric potential
Logarithmic amplifiers
Binary codes
Circuit simulation
Analog to digital conversion
Electric power utilization
Sampling

Keywords

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

    これを引用

    A logarithmic compression ADC using transient response of a comparator. / Inagaki, Yuji; Sugimori, Yusaku; Ioka, Eri; Matsuya, Yasuyuki.

    :: IEICE Transactions on Electronics, 巻 E100C, 番号 4, 01.04.2017, p. 359-362.

    研究成果: Research - 審査Article

    Inagaki, Yuji ; Sugimori, Yusaku ; Ioka, Eri ; Matsuya, Yasuyuki. / A logarithmic compression ADC using transient response of a comparator. :: IEICE Transactions on Electronics. 2017 ; 巻 E100C, 番号 4. pp. 359-362
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