### 抄録

This paper describes a logarithmic compression ADC using a subranging TDC and the transient response of a comparator. We utilized the settling time of the comparator for a logarithmic compression instead of a logarithmic amplifier. The settling time of the comparator is inversely proportional to the logarithm of an input voltage. In the proposed ADC, an input voltage is converted into a pulse whose width represents the settling time of the comparator. Subsequently, the TDC converts the pulse width into a binary code. The supply voltage of the proposed ADC can be reduced more than a conventional logarithmic ADC because an analog to digital conversion takes place in the time domain. We confirmed through a 0.18-μm CMOS circuit simulation that the proposed ADC achieves a resolution of 11 bits, a sampling rate of 20 MS/s, a dynamic range of 59 dB and a power consumption of 9.8 mW at 1.5 V operation.

言語 | English |
---|---|

ページ | 359-362 |

Number of pages | 4 |

ジャーナル | IEICE Transactions on Electronics |

Volume | E100C |

号 | 4 |

DOIs | |

State | Published - 2017 4 1 |

外部発表 | Yes |

### Fingerprint

### Keywords

### ASJC Scopus subject areas

- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering

### これを引用

*IEICE Transactions on Electronics*,

*E100C*(4), 359-362. DOI: 10.1587/transele.E100.C.359

**A logarithmic compression ADC using transient response of a comparator.** / Inagaki, Yuji; Sugimori, Yusaku; Ioka, Eri; Matsuya, Yasuyuki.

研究成果: Research - 審査 › Article

*IEICE Transactions on Electronics*, 巻 E100C, 番号 4, pp. 359-362. DOI: 10.1587/transele.E100.C.359

}

TY - JOUR

T1 - A logarithmic compression ADC using transient response of a comparator

AU - Inagaki,Yuji

AU - Sugimori,Yusaku

AU - Ioka,Eri

AU - Matsuya,Yasuyuki

PY - 2017/4/1

Y1 - 2017/4/1

N2 - This paper describes a logarithmic compression ADC using a subranging TDC and the transient response of a comparator. We utilized the settling time of the comparator for a logarithmic compression instead of a logarithmic amplifier. The settling time of the comparator is inversely proportional to the logarithm of an input voltage. In the proposed ADC, an input voltage is converted into a pulse whose width represents the settling time of the comparator. Subsequently, the TDC converts the pulse width into a binary code. The supply voltage of the proposed ADC can be reduced more than a conventional logarithmic ADC because an analog to digital conversion takes place in the time domain. We confirmed through a 0.18-μm CMOS circuit simulation that the proposed ADC achieves a resolution of 11 bits, a sampling rate of 20 MS/s, a dynamic range of 59 dB and a power consumption of 9.8 mW at 1.5 V operation.

AB - This paper describes a logarithmic compression ADC using a subranging TDC and the transient response of a comparator. We utilized the settling time of the comparator for a logarithmic compression instead of a logarithmic amplifier. The settling time of the comparator is inversely proportional to the logarithm of an input voltage. In the proposed ADC, an input voltage is converted into a pulse whose width represents the settling time of the comparator. Subsequently, the TDC converts the pulse width into a binary code. The supply voltage of the proposed ADC can be reduced more than a conventional logarithmic ADC because an analog to digital conversion takes place in the time domain. We confirmed through a 0.18-μm CMOS circuit simulation that the proposed ADC achieves a resolution of 11 bits, a sampling rate of 20 MS/s, a dynamic range of 59 dB and a power consumption of 9.8 mW at 1.5 V operation.

KW - ADC

KW - Latched comparator

KW - Logarithmic compression

KW - Settling time

KW - Subranging

KW - TDC

UR - http://www.scopus.com/inward/record.url?scp=85017384589&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85017384589&partnerID=8YFLogxK

U2 - 10.1587/transele.E100.C.359

DO - 10.1587/transele.E100.C.359

M3 - Article

VL - E100C

SP - 359

EP - 362

JO - IEICE Transactions on Electronics

T2 - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 4

ER -