### 抜粋

This paper describes a logarithmic compression ADC using a subranging TDC and the transient response of a comparator. We utilized the settling time of the comparator for a logarithmic compression instead of a logarithmic amplifier. The settling time of the comparator is inversely proportional to the logarithm of an input voltage. In the proposed ADC, an input voltage is converted into a pulse whose width represents the settling time of the comparator. Subsequently, the TDC converts the pulse width into a binary code. The supply voltage of the proposed ADC can be reduced more than a conventional logarithmic ADC because an analog to digital conversion takes place in the time domain. We confirmed through a 0.18-μm CMOS circuit simulation that the proposed ADC achieves a resolution of 11 bits, a sampling rate of 20 MS/s, a dynamic range of 59 dB and a power consumption of 9.8 mW at 1.5 V operation.

元の言語 | English |
---|---|

ページ（範囲） | 359-362 |

ページ数 | 4 |

ジャーナル | IEICE Transactions on Electronics |

巻 | E100C |

発行部数 | 4 |

DOI | |

出版物ステータス | Published - 2017 4 1 |

外部発表 | Yes |

### フィンガープリント

### ASJC Scopus subject areas

- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering

### これを引用

*IEICE Transactions on Electronics*,

*E100C*(4), 359-362. https://doi.org/10.1587/transele.E100.C.359