A low power matched filter for DS-CDMA based on analog signal processing

Masahiro Sasaki, Takeyasu Sakai, Takashi Matsumoto

研究成果: Article

6 引用 (Scopus)

抄録

This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.

元の言語English
ページ(範囲)752-757
ページ数6
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E86-A
発行部数4
出版物ステータスPublished - 2003 4
外部発表Yes

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Matched filters
Code division multiple access
Signal processing
Networks (circuits)
Electric power utilization
Digital to analog conversion
Capacitors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems

これを引用

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abstract = "This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.",
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AU - Sakai, Takeyasu

AU - Matsumoto, Takashi

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N2 - This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.

AB - This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.

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KW - DS-CDMA

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KW - Multiply-and-accumulate operation

KW - Spread spectrum

KW - Weighted-sum operation

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