A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc Hung LeTakumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa

研究成果: Conference contribution

19 引用 (Scopus)

抄録

A 32-bit CPU which operates with the lowest energy of 13.4 pJ/cycle at 0.35V and 14MHz, operates at 0.22V to 1.2V and with 0.14μA sleep current is demonstrated. The low power performance is attained by Reverse-Body-Bias- Assisted 65nm SOTB CMOS (Silicon On Thin Buried oxide) technology. The CPU can operate more than 100 years with 610mAH Li battery.

元の言語English
ホスト出版物のタイトルIEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII
出版者IEEE Computer Society
ISBN(印刷物)9781479938094
DOI
出版物ステータスPublished - 2014
イベント17th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2014 - Yokohama
継続期間: 2014 4 142014 4 16

Other

Other17th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2014
Yokohama
期間14/4/1414/4/16

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Program processors
Silicon
Oxides
Sleep

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Ishibashi, K., Sugii, N., Usami, K., Amano, H., Kobayashi, K., Pham, C. K., ... Manzawa, Y. (2014). A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. : IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII [6842954] IEEE Computer Society. https://doi.org/10.1109/CoolChips.2014.6842954

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. / Ishibashi, Koichiro; Sugii, Nobuyuki; Usami, Kimiyoshi; Amano, Hideharu; Kobayashi, Kazutoshi; Pham, Cong Kha; Makiyama, Hideki; Yamamoto, Yoshiki; Shinohara, Hirofumi; Iwamatsu, Toshiaki; Yamaguchi, Yasuo; Oda, Hidekazu; Hasegawa, Takumi; Okanishi, Shinobu; Yanagita, Hiroshi; Kamohara, Shiro; Kadoshima, Masaru; Maekawa, Keiichi; Yamashita, Tomohiro; Le, Duc Hung; Yomogita, Takumu; Kudo, Masaru; Kitamori, Kuniaki; Kondo, Shuya; Manzawa, Yuuki.

IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society, 2014. 6842954.

研究成果: Conference contribution

Ishibashi, K, Sugii, N, Usami, K, Amano, H, Kobayashi, K, Pham, CK, Makiyama, H, Yamamoto, Y, Shinohara, H, Iwamatsu, T, Yamaguchi, Y, Oda, H, Hasegawa, T, Okanishi, S, Yanagita, H, Kamohara, S, Kadoshima, M, Maekawa, K, Yamashita, T, Le, DH, Yomogita, T, Kudo, M, Kitamori, K, Kondo, S & Manzawa, Y 2014, A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. : IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII., 6842954, IEEE Computer Society, 17th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2014, Yokohama, 14/4/14. https://doi.org/10.1109/CoolChips.2014.6842954
Ishibashi K, Sugii N, Usami K, Amano H, Kobayashi K, Pham CK その他. A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. : IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society. 2014. 6842954 https://doi.org/10.1109/CoolChips.2014.6842954
Ishibashi, Koichiro ; Sugii, Nobuyuki ; Usami, Kimiyoshi ; Amano, Hideharu ; Kobayashi, Kazutoshi ; Pham, Cong Kha ; Makiyama, Hideki ; Yamamoto, Yoshiki ; Shinohara, Hirofumi ; Iwamatsu, Toshiaki ; Yamaguchi, Yasuo ; Oda, Hidekazu ; Hasegawa, Takumi ; Okanishi, Shinobu ; Yanagita, Hiroshi ; Kamohara, Shiro ; Kadoshima, Masaru ; Maekawa, Keiichi ; Yamashita, Tomohiro ; Le, Duc Hung ; Yomogita, Takumu ; Kudo, Masaru ; Kitamori, Kuniaki ; Kondo, Shuya ; Manzawa, Yuuki. / A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society, 2014.
@inproceedings{66de404a9d4f4d3486ca0abc0dbb98af,
title = "A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology",
abstract = "A 32-bit CPU which operates with the lowest energy of 13.4 pJ/cycle at 0.35V and 14MHz, operates at 0.22V to 1.2V and with 0.14μA sleep current is demonstrated. The low power performance is attained by Reverse-Body-Bias- Assisted 65nm SOTB CMOS (Silicon On Thin Buried oxide) technology. The CPU can operate more than 100 years with 610mAH Li battery.",
keywords = "CMOS, MCU, SOI, SOTB",
author = "Koichiro Ishibashi and Nobuyuki Sugii and Kimiyoshi Usami and Hideharu Amano and Kazutoshi Kobayashi and Pham, {Cong Kha} and Hideki Makiyama and Yoshiki Yamamoto and Hirofumi Shinohara and Toshiaki Iwamatsu and Yasuo Yamaguchi and Hidekazu Oda and Takumi Hasegawa and Shinobu Okanishi and Hiroshi Yanagita and Shiro Kamohara and Masaru Kadoshima and Keiichi Maekawa and Tomohiro Yamashita and Le, {Duc Hung} and Takumu Yomogita and Masaru Kudo and Kuniaki Kitamori and Shuya Kondo and Yuuki Manzawa",
year = "2014",
doi = "10.1109/CoolChips.2014.6842954",
language = "English",
isbn = "9781479938094",
booktitle = "IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII",
publisher = "IEEE Computer Society",

}

TY - GEN

T1 - A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

AU - Ishibashi, Koichiro

AU - Sugii, Nobuyuki

AU - Usami, Kimiyoshi

AU - Amano, Hideharu

AU - Kobayashi, Kazutoshi

AU - Pham, Cong Kha

AU - Makiyama, Hideki

AU - Yamamoto, Yoshiki

AU - Shinohara, Hirofumi

AU - Iwamatsu, Toshiaki

AU - Yamaguchi, Yasuo

AU - Oda, Hidekazu

AU - Hasegawa, Takumi

AU - Okanishi, Shinobu

AU - Yanagita, Hiroshi

AU - Kamohara, Shiro

AU - Kadoshima, Masaru

AU - Maekawa, Keiichi

AU - Yamashita, Tomohiro

AU - Le, Duc Hung

AU - Yomogita, Takumu

AU - Kudo, Masaru

AU - Kitamori, Kuniaki

AU - Kondo, Shuya

AU - Manzawa, Yuuki

PY - 2014

Y1 - 2014

N2 - A 32-bit CPU which operates with the lowest energy of 13.4 pJ/cycle at 0.35V and 14MHz, operates at 0.22V to 1.2V and with 0.14μA sleep current is demonstrated. The low power performance is attained by Reverse-Body-Bias- Assisted 65nm SOTB CMOS (Silicon On Thin Buried oxide) technology. The CPU can operate more than 100 years with 610mAH Li battery.

AB - A 32-bit CPU which operates with the lowest energy of 13.4 pJ/cycle at 0.35V and 14MHz, operates at 0.22V to 1.2V and with 0.14μA sleep current is demonstrated. The low power performance is attained by Reverse-Body-Bias- Assisted 65nm SOTB CMOS (Silicon On Thin Buried oxide) technology. The CPU can operate more than 100 years with 610mAH Li battery.

KW - CMOS

KW - MCU

KW - SOI

KW - SOTB

UR - http://www.scopus.com/inward/record.url?scp=84904643914&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84904643914&partnerID=8YFLogxK

U2 - 10.1109/CoolChips.2014.6842954

DO - 10.1109/CoolChips.2014.6842954

M3 - Conference contribution

AN - SCOPUS:84904643914

SN - 9781479938094

BT - IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII

PB - IEEE Computer Society

ER -