A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 μm complementary metal oxide semiconductor generation

Noriaki Oda, Shinya Ito, Toshiyuki Takewaki, Kazutoshi Shiba, Hiroyuki Kunishima, Nobuo Hironaga, Ichiro Honma, Hiroaki Nanba, Shinji Yokogawa, Akiko Kameyama, Takayuki Goto, Tatsuya Usami, Koichi Ohto, Akira Kubo, Mieko Suzuki, Yoshiaki Yamamoto, Susumu Watanabe, Kenta Yamada, Masahiro Ikeda, Kazuyoshi UenoTadahiko Horiuchi

研究成果: Article

9 引用 (Scopus)

抄録

A robust embedded ladder-oxide {k = 2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 μm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 μm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO 2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.

元の言語English
ページ(範囲)954-961
ページ数8
ジャーナルJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
46
発行部数3 A
DOI
出版物ステータスPublished - 2007 3 8

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wiring
Ladders
plugs
ladders
CMOS
Electric wiring
Oxides
oxides
electromigration
controllability
Metals
metals
flexibility
Electromigration
breakdown
capacitance
Metallizing
Controllability
Electric breakdown
copper

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)

これを引用

A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 μm complementary metal oxide semiconductor generation. / Oda, Noriaki; Ito, Shinya; Takewaki, Toshiyuki; Shiba, Kazutoshi; Kunishima, Hiroyuki; Hironaga, Nobuo; Honma, Ichiro; Nanba, Hiroaki; Yokogawa, Shinji; Kameyama, Akiko; Goto, Takayuki; Usami, Tatsuya; Ohto, Koichi; Kubo, Akira; Suzuki, Mieko; Yamamoto, Yoshiaki; Watanabe, Susumu; Yamada, Kenta; Ikeda, Masahiro; Ueno, Kazuyoshi; Horiuchi, Tadahiko.

:: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 巻 46, 番号 3 A, 08.03.2007, p. 954-961.

研究成果: Article

Oda, N, Ito, S, Takewaki, T, Shiba, K, Kunishima, H, Hironaga, N, Honma, I, Nanba, H, Yokogawa, S, Kameyama, A, Goto, T, Usami, T, Ohto, K, Kubo, A, Suzuki, M, Yamamoto, Y, Watanabe, S, Yamada, K, Ikeda, M, Ueno, K & Horiuchi, T 2007, 'A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 μm complementary metal oxide semiconductor generation', Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 巻. 46, 番号 3 A, pp. 954-961. https://doi.org/10.1143/JJAP.46.954
Oda, Noriaki ; Ito, Shinya ; Takewaki, Toshiyuki ; Shiba, Kazutoshi ; Kunishima, Hiroyuki ; Hironaga, Nobuo ; Honma, Ichiro ; Nanba, Hiroaki ; Yokogawa, Shinji ; Kameyama, Akiko ; Goto, Takayuki ; Usami, Tatsuya ; Ohto, Koichi ; Kubo, Akira ; Suzuki, Mieko ; Yamamoto, Yoshiaki ; Watanabe, Susumu ; Yamada, Kenta ; Ikeda, Masahiro ; Ueno, Kazuyoshi ; Horiuchi, Tadahiko. / A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 μm complementary metal oxide semiconductor generation. :: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 2007 ; 巻 46, 番号 3 A. pp. 954-961.
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AU - Kunishima, Hiroyuki

AU - Hironaga, Nobuo

AU - Honma, Ichiro

AU - Nanba, Hiroaki

AU - Yokogawa, Shinji

AU - Kameyama, Akiko

AU - Goto, Takayuki

AU - Usami, Tatsuya

AU - Ohto, Koichi

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AU - Suzuki, Mieko

AU - Yamamoto, Yoshiaki

AU - Watanabe, Susumu

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AU - Ikeda, Masahiro

AU - Ueno, Kazuyoshi

AU - Horiuchi, Tadahiko

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N2 - A robust embedded ladder-oxide {k = 2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 μm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 μm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO 2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.

AB - A robust embedded ladder-oxide {k = 2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 μm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 μm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO 2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.

KW - 0.13μm node

KW - CMOS

KW - Complementary metal oxide semiconductor

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KW - Ladder-oxide

KW - Low-k

KW - Single damascene

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