A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface

Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahir Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura

研究成果: Conference contribution

1 引用 (Scopus)

抄録

A scalable heterogeneous multi-core processor is developed. 3D heterogeneous chip stacking of a general-purpose CPU and reconfigurable multi-core accelerators improves computational energy efficiency by proper task assignment and massive parallel computing. The stacked chips interconnect through a scalable 3D Network on Chip (NoC). By simply changing the number of stacked accelerator chips, processor parallelism can be widely scaled. In combination with Dynamic Voltage and Frequency Scaling (DVFS), the energy efficiency can be optimized for various performance requirements. No design change is needed, and hence no additional Non-Recurring Engineering (NRE) cost. An inductive-coupling ThruChip Interface (TCI) is applied to stacked-chip communications, forming a low-cost and robust high-speed 3D NoC. A prototype demonstration system has been developed with 65nm CMOS test chips. Successful system operations including lO-hours continuous Linux OS operation are confirmed for the first time.

元の言語English
ホスト出版物のタイトルIEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI
DOI
出版物ステータスPublished - 2013
イベント16th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2013 - Yokohama
継続期間: 2013 4 172013 4 19

Other

Other16th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2013
Yokohama
期間13/4/1713/4/19

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Particle accelerators
Energy efficiency
Parallel processing systems
Program processors
Costs
Demonstrations
Communication
Network-on-chip
Voltage scaling
Linux
Dynamic frequency scaling

ASJC Scopus subject areas

  • Hardware and Architecture

これを引用

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., ... Nakamura, H. (2013). A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface. : IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI [6547916] https://doi.org/10.1109/CoolChips.2013.6547916

A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface. / Miura, Noriyuki; Koizumi, Yusuke; Sasaki, Eiichi; Take, Yasuhiro; Matsutani, Hiroki; Kuroda, Tadahir; Amano, Hideharu; Sakamoto, Ryuichi; Namiki, Mitaro; Usami, Kimiyoshi; Kondo, Masaaki; Nakamura, Hiroshi.

IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 2013. 6547916.

研究成果: Conference contribution

Miura, N, Koizumi, Y, Sasaki, E, Take, Y, Matsutani, H, Kuroda, T, Amano, H, Sakamoto, R, Namiki, M, Usami, K, Kondo, M & Nakamura, H 2013, A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface. : IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI., 6547916, 16th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2013, Yokohama, 13/4/17. https://doi.org/10.1109/CoolChips.2013.6547916
Miura N, Koizumi Y, Sasaki E, Take Y, Matsutani H, Kuroda T その他. A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface. : IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 2013. 6547916 https://doi.org/10.1109/CoolChips.2013.6547916
Miura, Noriyuki ; Koizumi, Yusuke ; Sasaki, Eiichi ; Take, Yasuhiro ; Matsutani, Hiroki ; Kuroda, Tadahir ; Amano, Hideharu ; Sakamoto, Ryuichi ; Namiki, Mitaro ; Usami, Kimiyoshi ; Kondo, Masaaki ; Nakamura, Hiroshi. / A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface. IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 2013.
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